[time-nuts] Question concerning failure and value of HP 5371A
Arnold.Tibus at gmx.de
Sat Oct 15 19:36:51 EDT 2005
Hi Hal, thanks for your hints!
On Sat, 15 Oct 2005 12:38:56 -0700, Hal Murray wrote:
>> The point is, I do not find gates capable to work well beyond 30, 40
>> MHz. I there somebody having a helpful idea how this could be solved?
>How fast do you want to go? Modern FPGAs are loafing at 100 MHz.
I would like to experiment with 1 ns or 2 ns pulses and gates capable to count
such pulses, meaning with bin. counters able to work with 250 MHz or
up to 500 MHz clock in signal. That speed just for that 2 primary elements
of a (high speed) counter. Am I dreaming? I like it.
I thought that this should be possible in times with GHz PCs...?
>A major problem at high speeds is signal integrity. You can't toss something
>together with proto-board technology. You need a good ground plane and power
>supply decoupling. (and they generally require several power supplies)
That is v e r y clear, I am preaching since decades of years to all the
'digitals', that as well for digital circuit design you have to know and respect
all the physics for RF, as it is even worse: digital signal transmission even on CBs
is not just switching dc on and off (combined with mathematics), but it is
w i d e b a n d RF, not so easy to match the lines and stages properly as
for 'normal' RF circuits with small bw.!
We are arriving the moment that one need to be both experts, analog RF and digital.
Impedance matching everywhere, excelent returns (gnd), good rf-shielding and
blocking together with stiff and rf-resistant pwr-supplies are stringent, a must.
>If you want to get started with FPGAs, the Spartan-3 starter kit at $100 is a
>pretty good package. You can get it from Xilinx or Digilent
>It's got a 50 MHz osc. (Beware, the connectors around the edge don't have
>enough ground pins for serious high speed work.)
>Peter Alfke, chief apps wizard at Xilinx, has made a hobby out of using FPGAs
>for things like measuring pulse duration and/or frequency. He's posted
>several neat ideas on comp.arc.fpga over the years. They may be hard to find
>- "counter" is a popular term.
I would like to get some more infos about that ideas.
>The latest trick that I remember is to use the high-speed SERDES logic on
>newer chips to sample a raw signal. You get 20 bits in parallel with a
>sample rate of 2 GHz. Then slower logic can count the transitions or
> Message-ID: <BC8772E1.5C19%peter at xilinx.com>
Many thanks again Hal, I will look in that direction.
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