[time-nuts] Interfacing a 8dBm sine output of an OCXO to adigitallogic standard
Richard (Rick) Karlquist (N6RK)
richard at karlquist.com
Fri Sep 16 11:07:40 EDT 2005
> I can imagine that the sine wave must be squared off
> > using a fast comparator and then fed through to a logic
> > driver. Are there any integrated IC's out there that does
> > this? It would be rather sad to sustain substantial phase
> > noise degradation due to a floating comparator threshold and
> > limited slew rate.
> > Stephan Sandenbergh
A comparator IC is the worst possible circuit you could use.
Especially a fast one. Fast comparators have higher analog
bandwidth, which means a greater noise bandwidth for the
purpose of noise aliasing. Also, the propagation delay of
comparators is very temperature and amplitude dependent
(ie AM to PM noise conversion).
The simplest circuit that is any good is to simply capacitively
couple the sine wave into the clock input of a 74ACXX series logic
gate. Use 10K resistors to ground and +5V to DC bias the
input to +2.5V. Do NOT use 74HCXX logic for this.
We used the 74ACXX trick in the HP/Agilent/Symmetricom 5071A
cesium clock at 80 MHz, although it was not in a place that
needed extremely low phase noise.
The best circuits involve using bandlimited, low distortion,
low phase noise amplifiers to produce a large sine wave which
is then passively limited with diodes.
You can also get away with driving a differential pair with
a common current source for the emitters.
A classic paper on zero crossing detectors by JPL's John Dick
at the 1990 PTTI explains the theory behind all this.
Rick Karlquist N6RK
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