[time-nuts] Gate propagation delay jitter
cfmd at bredband.net
Thu Apr 12 04:58:28 EDT 2007
From: Enrico Rubiola <rubiola at femto-st.fr>
Subject: Re: [time-nuts] Gate propagation delay jitter
Date: Wed, 11 Apr 2007 17:15:13 +0200
Message-ID: <D8508E7D-37CF-46BE-A349-5C351D6EFD36 at femto-st.fr>
> Dear all,
> I mean that the right way to reduce the jitter of a digital circuit is
> to re-synchronize the output to the main clock with a D-type
> flip-flop (no other types).
That is natural and comes almost without saying. Assuming you have a low jitter
synchronous clock to start with.
> The right way to measure the jitter looks like the attached sketch.
> The important point is to respect the timing of the D-FF.
> There is no reason to divide the frequency.
> Metastability is not an issue.
Not even when you have timed your D input in a particularly bad place timing-
My point about metastability was in interpolating counters where the coarse
clock samples the signal (which can take any timing relation to the clock) and
the resulting error signal will include timing variations of that DFF. The
traditional trick to use two DFFs in series may be advisable unless you have
secured the metastability risk by other means.
> Respect the quadrature condition at the mixer inputs.
> May need a buffer at the FF output
> Attached also the Egan's article. Walls, I'll search
OK. Thanks! Will read!
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