[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
bruce.griffiths at xtra.co.nz
Tue Dec 11 20:53:57 EST 2007
Luis Cupido wrote:
> Hi Bruce and Scott.
> >> What about sampling both the VXCO and 1PPS at a 200MHZ rate?
> >> That should determine the phase difference within no more than a 10ns
> >> inaccuracy.
> Simplicity is good but when using a CPLD or an FPGA no need to get
> simple if a better design still fits inside the chip ;-)
> Indeed those style of phase measuring schemes have far better
> performance than the simple flip flop or similar.
Not true, the effective measurement noise is only a few percent less
than that of a single bit phase detector (D flipflop) better with an
infinite resolution phase detector so why bother.
Single bit and 3 level ADCs are widely used in radio astronomy as except
when interference is a problem, multibit ADCs offer no significant
> I say this because I had all the logic on a CPLD to play with
> so I tried a large number of phase locking schemes and
> could compare them.
By all means try them, but why add the power consumption and complexity
of a CPLD if it offers little improvement in performance?
> First of all the lock capture range can become a bit
> independent of the integration time with a proportional phase lag
> counting method. Some counting methods will inherently search for lock
> when lock is lost. Some of those methods also have lock acquisition
> times orders of magnitude smaller.
> On the other hand on CPLD (or FPGA) complexity doesn't cost more as
> this stuff is ultra extra small considering the size of
> a today's CPLD (eg. maxII w/ 1570 macrocells). No matter what you do
> a medium CPLD will be only used 10 to 20% not more.
If you are going to use a CPLD you should also implement the processor
in the gate array as this reduces the PCB wiring complexity considerably.
> What I use on the reflock II is a time lag counter from the 1pps to
> next clock, and this value drive a dac. Only a small integration time
> is done digitally and the large integration time if one requires that
> is done with a classical R and C without any active components right
> before the Vtune of the VCXO. Therefore not a big DAC resolution is
> required (I use 12-14bit) since the averaging is on the outside in an
> analog filter in which simple 64 seconds integration time will grant
> you 6 bit more resolution.
Trying to do all the filtering with an analog filter restricts the range
of loop response times to relatively small values degrading the
performance of the better OCXOs considerably.
Achieving time constants of 100 sec or more is somewhat
expensive/impractical using resistors and capacitors.
Some analog filtering is required but most of the long term filtering
should be done by the processor.
> It may look a strange combination of a modern devices and a old
> fashioned filter but it had by far outperformed all the designs I could
> test w/ microporcessors + dac (in which some noise did get through),
> or lack stability.
Layout and isolation of the DAC from processor created noise are critical.
> Luis Cupido
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