[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
cupido at mail.ua.pt
Wed Dec 12 05:37:08 EST 2007
Fine, you don't like the words "far better performance"... okay ;-)
you do recognize the small advantage in noise but
gave no relevance to the other aspects namely the
lock acquisition, the fact that I can monitor the jitter over time
etc. (all of them were contained in my word "performance"
not just the noise).
> By all means try them,
Humm?! I did tried them, that's exactly what I said !!!
Note that I do have the hardware on a CPLD so schemes
can be done on type-compile-and-test basis without
soldering wires hi ;-)
> but why add the power consumption and complexity
> of a CPLD if it offers little improvement in performance?
Geeee, using a CPLD does not add complexity, it is just one chip
and it offers the commodity of being easily configured etc.
Also the power consumption is surely not an issue, if you
are not happy with the 50 to 100mA you may draw from 3.3v
just use a low power CPLD (like tha maxIIZ) and get
only 10 to 20mA.
On the comments about the filter and bandwidth I do agree
with you it would be good to have most of it digital
(doesn't need to be necessarily on a CPU... inside the CPLD
is the same) I do have versions with integration also
in digital and I'm still in the process of improving it.
I believe I may get rid off of some of the inconvenient
analog filtering, in the next VHDL iterations hi ;-)
One thing is puzzling me, if you suggest using a
single D flip-flop and want it simple as you say
I presume you have also to filter in analog ?!
So you end up with a slightly worst phase comparator
and the less convenient analog filter :-(
Or do you need to add a microcontroller and a DAC ?
If that is the case, there goes off your complexity issue
much higher than a simple CPLD.
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