[time-nuts] Software Sawtooth correction prerequisites?
Dr Bruce Griffiths
bruce.griffiths at xtra.co.nz
Sat May 12 05:00:08 EDT 2007
Tom Clark, K3IO wrote:
>> Why add the cost of a programmable delay line when the additional cost
>> of correction is a few lines of code?
>> They also don't remove the requirement for subnanosecond phase
>> measurement resolution and accuracy.
> But the receiver itself has intrinsic noise at the nsec level. You are
> better off by averaging sawtooth corrected (either hardware or software)
> measurements to achieve sub-nsec precision; IMHO, sub-nsec individual
> measurements aren't needed. Surely you don't plan to tweak a GPSDO every
> second! A good xtal is much better than ANY GPS rcvr on times of 1-100 sec.
>> Whilst an analog phase lock loop can have the necessary resolution
>> they are somewhat impractical for the relatively long averaging times
>> required when optimally disciplining a good OCXO.
>> The computational load isnt that severe as you only make one phase
>> measurement per second.
>> One of the simplest ways of achieving subnanosecond phase measurement
>> resolution is to feed a quadrature phase 10MHz sinewave into a pair of
>> simultaneous sampling ADCs (MAXIM have suitable devices prices seem
>> reasonable). The sinewaves are sampled at the leading edge of the GPS
>> receiver PPS signal.
>> The ADC outputs can then be used to determine where in the cycle the
>> PPS edge occurred. This in effect is a subnanosecond resolution phase
>> detector with a range of 100nsec. The range can easily be extended by
>> using a small CPLD which incorporates a couple of synchronisers (one
>> clocked by the positive slope transition of the 10MHz signal and the
>> other clocked by the negative slope xero crossing transition of the
>> 10MHz signal) The output of both synchronisers samples the value of a
>> synchronous counter which is clocked by the positive slope zero
>> crossing of the 10MHz sinewave. Software then sorts out which latched
>> count is most reliable (the synchroniser whose clock edge is furthest
>> from the PPS transition). This sounds complex but it isnt, especially
>> if you select the right PIC (or other micro) with built in counters
>> (PIC18F4550?) that can be sampled by an external transition (output of
>> a synchroniser). The counter need only be an 8 bits counter.
> This sure sounds like a more complicated measurement than is necessary
> to me. If you have a 10 MHz oscillator, simply feed it into the "D"
> input into a latch clocked by the de-sawtoothed GPS 1PPS. The output of
> the latch is a 0 or 1 depending on the precise phase of the oscillator.
> You want this latched 0/1 measurement to average to ½ over a long term
> (seconds). As the statistics deviate from a 50/50 split, you tweak the
> oscillator. The ~1 nsec of residual noise from the sawtooth corrected
> GPS rcvr acts a natural dither. No counters, no ramps, no big A/D
> converter -- it couldn't be simpler! And if the 10MHz (=> 100 nsec phase
> ambiguity) is too fine for your oscillator, then divide it to 5 MHz
> (=>200 nsec) or 1 MHz (=> 1µsec). This should be good enough to pull in
> a xtal that is off by 1:10e6.
Very nice technique, much better to make use of the receiver noise if
In this case hardware correction of the PPS error is of course essential.
In essence this technique implements a servo with a narrow proportional
band of a few nanoseconds the width of the proportional band being
determined by the corrected PPS signal noise characteristics.
Outside the proportional band the servo saturates but retains the sign
of the phase error.
As the noise of the receiver increases so does the width of the
How then does one then actually measure the receiver timing noise, if
one wishes to detect when it deteriorates to a point where it is prudent
to go into holdover mode?
Perhaps a chain of (3) flipflops whose D inputs are driven by the OCXO
derived (10MHz, IMHz, etc) frequency and the clock inputs of which are
driven by successively delayed (stable delay) versions of the PPS edge.
For example the first flipflop is clocked by the PPS edge, the second
fliflop is clocked by the PPS edge delayed by say T ns, and the third
flipflop is clocked by PPS delayed by 2T ns.
Follow these flipflops by a set of synchronisers. Lock the OCXO so that
the 2nd Flipflop has 50% probability of being either 1 or 0. The
probability of occurrence of say a logic 1 at the outputs of the other
first and third flipflops can then be used to monitor the receiver
timing noise level. Alternatively the D inputs to the flipflops could be
successively delayeed by T ns whilst all flipflops are clocked by the
Surely it would be better to use a synchroniser and/or a flipflop/latch
with extremely short regeneration time constant to ensure that the
probability of metastable states is insignificant.
In this case subsequent stages of the synchroniser could be clocked by
delayed (fixed non critical delay) versions of the PPS transition as
waiting several seconds for a particular decision to propagate to the
output of the synchroniser if each synchroniser stage (D flipflop ) is
clocked by the PPS signal may be undesirable. Although a 2 or 3 stage
PPS clocked synchroniser would only have a delay of 3 seconds or so.
Using a 2 stage PPS clocked synchroniser should make the metastable
state probability at the output of the second flipflop insignificant
even if one used relatively slow HCMOS.
The question of the effect of any asymmetry of the decision statistics
of the first flipflop remains.
Since the PPS edge is being adjusted so that it has a high probability
of occurring within a few nanoseconds of the OCXO clock edge the
standard formula for calculating the metastability characteristics
doesn't apply the effective frequency of the 10MHz clock is in effect
much higher (200MHz??) for the purposes of metastability calculations.
Instead of using such a fudge factor its better perhaps to use a more
fundamental analysis to determine the metastable state probability a
little more accurately.
There is little enough information available on the metastability
characteristics of particular flipflops let alone the symmetry of the
However one should remember that even ADC's (particularly flash ADCs)
exhibit "sparkle" codes so they are not immune to metastability effects.
It may still be necessary to have some way of detecting "missing" PPS
>> Another technique is to start a ramp on the leading edge of the PPS
>> signal from the GPS receiver and stop it at the corresponding output
>> transition of a synchroniser (clocked at 10MHz) whose output samples
>> an (8bit) counter (also clocked at 10MHz - your local OCXO standards
>> frequency). The final value of the ramp is sampled by an ADC and
>> combined with the sampled count to resolve the 1 count ambiguity at
>> the synchroniser output. The ramp is then reset for the next PPS
>> pulse. Calibration of the ramp generator is required but calibration
>> cycles are easily interleaved between PPS pulses.
>> Although it may seem that a fast opamp is required for the ramp
>> generator, this isnt so as you can wait for any opamp (and/or ADC
>> input) to settle to before sampling the ramp output.
>> With careful design curvature correction isn't required (don't
>> slavishly copy the Linear technology Application note, you can do
>> better with less). The ramp generator needs a range of 300ns or
>> greater with a 10MHz synchroniser clock. A 10-12 bit ADC will provide
>> subnanosecond resolution. The ADC need not be fast (10us per
>> conversion is adequate), however a sigma delta ADC is unsuitable.
> This also strikes me as a more complicated implementation than is
> needed. But then, I prefer beer and white zinfandel wine too.
> I hope these comments helped a bit -- 73, Tom
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