[time-nuts] time-nuts Digest, Vol 38, Issue 6
ve2zaz at yahoo.ca
Thu Sep 6 11:26:48 EDT 2007
I appreciate the time you put in providing feedback. Your points are well noted and some of them will be applied in any subsequent design.
Regarding throwing away the sample while the OCXO is stabilizing, I don't agree with your statement. While it might not hurt to leave it in there, I don't see the harm done by removing it. The averaging period lasts for a few hours, so doing an average of "known stable" samples to me is the way to go. I don't see the information contained in that dropped sample as valuable, as it would be if the time constant were fast. You are probably looking at it from the angle of a continuous frequency/phase adjustment as an analogue loop and discrete PC would do it...
Regarding DAC vs PWM, I agree with your statement. The decision I took was to try to decrease the number of components (and cost) while still achieve a decent performance. Of course you and I have a different definition of "decent", but that's OK. ;-)
The PCB is a double-side one. Even though I would have preferred to pour a ground plane on an entire layer, once routing was over, there was not much gain left in doing so. Only small isolated islands of copper would have shown. A four-layer PCB would have been better but much more expensive.
I wish I could make a good sigma-tau measurement, but I don't have easy access to a known good reference and a very good T.I. counter. My HP 5328A would not cut it, or would it? How would a HP 53131A do? We have an HP Phase noise test set (entire rack) at work, it might be possible to use it...
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To: time-nuts at febo.com
Sent: Wednesday, September 5, 2007 12:00:01 PM
Subject: time-nuts Digest, Vol 38, Issue 6
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1. Re: GPSDO Question (Bruce Griffiths)
> He everyone,
> Just a few points/questions I would like to make regarding the discussion FLL vs PLL vs my design.
> One question that I have is regarding FLL vs PLL. The statement that a PLL is better than a FLL on a GPSDO may make sense when looked at from an analog loop and discrete phase comparator signal perspective, but what about the software that closes the loop? For example, the software may provide the ability to not make a frequency adjustment if the frequency difference (or phase difference) is too small. How does this come into play when comparing the two approaches? In other words can we make the software-based FLL a better perfromer so that the claim that PLL is better may not be as obvious?
Throwing away information as you suggest almost invariably degrades
You could improve your system somewhat by eliminating the 16 second
blanking period whilst you wait for the OCXO to settle.
This delay is unnecessary, a stable loop is possible without it.
The point of the loop is to stabilise the OCXO frequency not to measure
it as accurately as possible.
Using a PWM DAC as you have is almost never a good idea as the PWM
modulation frequency components need to be attenuated by at least 120dB
to avoid significantly degrading the OCXO performance via low level
modulation of the OCXO frequency by the residual PWM signal. Your simple
low pass filter is unlikely to achieve this. Using a conventional DAC
(suitable 16 bit DACs are relatively inexpensive these days) minimises
this problem, however if it is dithered the dither modulation frequency
components need to be attenuated to below the OCXO noise level. If the
dither amplitude is only a few bits (it should almost always be greater
than 1 bit) then filtering the dither components is a somewhat easier
proposition as 60dB attenuation or so should be adequate (with a 16 bit
DAC). However feedthrough from the DAC digital control signals also has
to be attenuated adequately, this is a more difficult but potentially
Did you actually use a ground plane on your PCB?
Removing the frequency dividers from the board should also improve
performance as they are yet another source of unwanted modulation
frequencies for the OCXO EFC input.
Ideally you should use a distribution amplifier to feed various systems
such as the FLL system and any such dividers a well shielded enclosure.
> Finally, just a reminder: I make no claim of mind-blowing
> performance with my design. From the beginning, it has been clearly stated
> that the expected short term accuracy of the VE2ZAZ design (assuming a
> decent OCXO is used) should be better than 1x10^-9. My website also
> provides the same information. The feedback that I have received from
> the users correlate with this. I like to see my work as allowing the 100+ users to learn more about disciplining an oscillator and obtain a better 10MHz reference. Nothing more than this.
Your performance measures are less than satisfactory for an informed
decision of whether the performance is adequate for a particular purpose.
Plots of the Allan deviation versus tau are desirable as well as some
idea of the level of any incidental sidebands.
Achieving an accuracy of 1E-9 with a 10811 or similar OCXO is about
10-100 times worse than can be achieved with a relatively inexpensive
PLL disciplining technique.
Surely if an accuracy stability of 1E-9 is adequate a lower performance
(and cheaper) oscillator would suffice.
> Bert, VE2ZAZ
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