[time-nuts] 5 MHZ PIC PPS Divider?

[Bruce Griffiths]

Brooke Clarke wrote:
> Hi Bruce:
>
> The A/D used is only 12 bits @ 300 kHz and Linear now has very similar 12 bit 
> A/D at 600 kHz and 24 bit much slower.  Since a s/h is used to capture the ramp 
> value the key spec seems to be that the hold time exceeds the conversion time. 
>   Are there s/h circuits that hold for more than 130 ms?
>
> Hard to say what "hold" means when talking about 24 bit conversions.  I'm not 
> sure of how droop would effect the result.
>
> I'm asking because the LTC2400 is about $8 compared to the LTC1273A for $25.
>
> Have Fun,
>
> Brooke Clarke
>   
Brooke

You would need a separate buffered sample and hold when using an LTC2400 
or similar sigma delta  ADC as opposed to a capacitive charge 
redistribuiton ADC like the LTC1273 and its successors.
Perhaps the best way to extend the hold time is to resample the analog 
voltage with a slower acquisition time low leakage sample and hold circuit.
Since the output is unipolar one could just ramp up an integrator until 
its output is equal to the voltage across the TAC capacitor.

The LTC2400 has a periodic switched capacitor input so that it 
approximates a resistive load, thus the TAC output needs to be buffered.

If you use guard rings etc the TAC leakage/discharge current may be 
around 100pA or so with a runup current of say 5mA. Thus discharge time 
for a 400ns full scale input will be around 20secs.
Droop as long as its linear wont affect conversion linearity however it 
will affect the TAC gain.
You would need to use a very low bias current buffer to drive the 
LTC2400, however its settling time can be quite slow.
It would also be possible to use an modified integrator with a large 
shunt input cap for temporary charge storage whilst the integrator settles.

I suspect it would be better to use a cheaper more modern charge 
redistribution ADC like an LTC1415 or similar.

Bruce