[time-nuts] Phase Noise/Jitter/SNR/N to Slope ratio etc
Don Collie jnr
merdon at xtra.co.nz
Tue Apr 29 01:27:35 EDT 2008
So to summarise : To make a synthesiser`s phase noise low :
- Apply the KIS principle [Keep It Simple]
- Use high speed [non-saturating?] logic rather than low
- The logic supplies should be well regulated, distributed
- Make the PRF to the P/F detector as high as possible.
- The loop filter should have a sharp rolloff
.... and maintain loop stability ;-)
- The loop BW should be as low as possible.
[ ie loop filter should rolloff at the lowest frequency
- The reference frequency should have the highest slope to
noise ratio possible Since slope is proportional to
amplitude if frequency is constant, then this ratio
equates to a high SNR - and we all might as well
go shoot ourselves if the reference frequency
changes - eh guys ;-).
- Use quality, low noise, components in the VCO including
the active device.
- Employ great craftiness in the choice of circuit
configuration for the VCO.
- The VCO resonant circuit should be of the highest
"Q" possible - Why?
- Use a YIG in preference to Varicaps, and use back-to-
back matched varicaps if possible.
- Use great care with PSU, and earth returns between the
digital [phase detector] circuits, and analogue
circuits [ VCO].
-The VCO supply Voltage needs to be very clean, and
- Minimise the tuning range of the VCO where possible
to minimise the effect of any jitter that *does*
reach the VCO through the loop filter.
- Keep the RF Voltage across the varicaps small
[class "A" oscillator?/crafty design]
- Maximise the VCO output voltage to maximise SNR
or output amplitude to phase noise amplitude.
Some of these are at odds with each other, but can anyone
constructively criticise or refute these points, or add more, or expand on any of them, please?
Again, thankyou for your thoughts,.......................Don C.
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