[time-nuts] Sub Pico Second Phase logger
joegwinn at comcast.net
Mon Dec 22 18:16:24 UTC 2008
At 2:01 AM +0000 12/22/08, time-nuts-request at febo.com wrote:
>Date: Mon, 22 Dec 2008 11:19:06 +1300
>From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
>Subject: Re: [time-nuts] Sub Pico Second Phase logger
>To: Discussion of precise time and frequency measurement
> <time-nuts at febo.com>
>Joe Gwinn wrote:
> > Bruce,
>>>>> Some claim to be able to sync to an SPDIF input but the resultant jitter
>>>>> may be large.
>>>> Why large jitter? Bad implementation?
>>> I'm just suspicious, although I did see some data somewhere that seemed
>>> to confirm my suspicions.
>>> The S/PDIF signal has to be a valid SPDIF signal not just a square or
>>> sine wave clock.
>>> Output sample rates (for the AP192) are then identical to that of the
>>> the S/PDIF source which is limited to
>>> 192, 176.4, 96,88.2 48, 44.1 32 KSPS.
>> I did a little looking. I bet that the sync quite well, but this
>> signal is pretty complex. One assumes that there is a box that takes
> > in a 10 MHz ref and does the rest, because the broadcast industry
>> does use atomic clocks.
>Ulrich has built a circuit that takes a sampling frequency input derived
>from a 10MHz GPSDO output and produces an S/PDIF output for this
>Its certainly worth trying since all the specs for the sound card aren't
Ulrich posted some details, and I got the datasheet for study.
But I bet someone already makes the necessary box.
> >>>> Conventional Diophantine synthesis uses number theory
>together with 2 or
>>>>> 3 conventional synthesiser loops to achieve very fine resolution whilst
>>> >> maintaining a high PLL phase detector input frequency.
>>>> In a sense, the concatenated DDS approach is a divide-and-mix chain.
>>> > Perhaps there is a parallel here.
>>> The DDS based equivalent (of the dual PLL Diophantine synthesiser) would
>>> use a pair of DDS chips each replacing a conventional PLL in the
>>> Diophantine frequency synthesiser, the output frequency of each having
>>> zero phase truncation spurs.
>>> Both DDS clock sources should be spur free and have a frequency ratio
>>> that is a selected fixed rational fraction.
>> A M/N PLL chip can arrange this. I recall that Silicon Labs makes
>> such a chip, which requires a parameter load on power-up, so a
> > computer or FPGA is needed.
Also of interest:
>M and N only have to be relatively prime (ie the GCD of M and N is 1).
>The ratio of M/N should also be close to 1.
>If the spacing of the phase truncation spur free output frequencies is
>about 10kHz (for either DDS) and M, N ~ 1000 the resultant mixer output
>frequencies would have a spacing of about 10Hz which may be adequate for
I found and read the basic articles, which can be downloaded from
Prof Sotiriadis' website:
Items J10, J13, and J15 seem particularly relevant.
All one needs is the M/N chip, although one can certainly use DDS chips.
> >> A conventional mixer would then be used to either add or subtract the
>>> two DDS output frequencies.
>>> If the ratio of the 2 DDS clock source frequencies is appropriately
>>> chosen the spacing between the resultant mixer output frequencies can be
>>> much finer than the spacing between the truncation spur free outputs of
>>> either DDS chip.
>>> The DDS and mixer outputs should be filtered to remove harmonics and
>>> other unwanted frequencies.
>> If the DDS chips are well chosen, we will get sin and cos outputs,
>> and so can implement a dual-mixer phasing scheme to yield only the
>> sum frequency or only the difference frequency, greatly reducing the
>> amount of filtering needed. The better balanced the channels are the
> > better the cancellation of the unwanted term. This is basically the
> > phasing method of single-sideband signal generation.
This would be a reason to use DDS chips instead of M/N PLL chips,
unless there are M/N PLL chips that provide quadrature outputs.
SiLabs Si5338 may suffice, as it allows one to control the relative
phase of its outputs.
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