bruce.griffiths at xtra.co.nz
Sun Jan 20 23:44:25 EST 2008
Didier Juges wrote:
> A Johnson counter set to recycle at a count of 3 (by tying Q3 to Clear)
> should have low noise, at least as long as you use output Q2 since Q3 (and
> then Q1) will be affected by the time for the chip to clear..
Using an asynchronous clear on an otherwise synchronous counter isnt a
particularly good idea unless you have no other choice.
Its easy enough to configure the counter to be fully synchronous so that
it only takes one cycle to exit the unused state which it should only
enter on startup or as the result of a transient event (on the power
supply asynchronous preset and clear etc) . JK flipflops are more
flexible than D flipflops when designing divide by 3, 5.6.7 etc circuits.
The divide by 3 circuit using JK fliflops actually works with no lock up
in an unused state as shown in my later post.
> In a related subject, I made some spectrum analyzer screen shots of various
> duty cycle pulsed signals.
> I had actually planned to do some of that a while ago to illustrate the
> effect of duty cycle on switching supply spurious emissions. This thread
> actually prompted me to finish that test. Thanks!
> Here are the plots:
> Didier KO4BB
Nothing like actual measurements to fully convince some.
Now a demo of the fact that even harmonic lobes of an FM signal are in
fact the same that would be produced by AM of the carrier at these
harmonics of the modulation frequency would be nice.
You could also show the actual baseband spectrum at the output of a
phase detector with various input signals.
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