[time-nuts] Frequency Divider
magnus at rubidium.dyndns.org
Fri Apr 3 07:32:02 UTC 2009
Hal Murray skrev:
>> Start with a buffer amp and then a decent Schmidt trigger.
> If you have a clean input signal, a Schmitt trigger doesn't solve any
> problems. It does help if you have a slowly rising signal such that noise
> might be significant while the signal is near threshold. A 10 MHz sine wave
> is slow relative to AC logic.
> Since we were recently speaking of LPROs, their user manual has a section on
> how to convert 10 MHz sine waves into TTL signals. None of their suggestions
> used Schmitt triggers.
Schmitt triggers seems to be misunderstood by many. They do NOT
magically solve all issues with noise in the correct way. It seems
strange that one actually has to say that, but it seems to be a widely
accepted fact that if one uses a schmitt trigger one is doing the right
thing. The answer is really maybe, it depends. There are many things
where it is just what should be used. For trigger signals where jitter
may be of concern you can do better. If the signal first hits a Schmitt
trigger, then the noise will modulate the trigger point with the
achieved slope at that stage, and no further processing will improve on
that but a full sufficiently narrow bandwidth PLL. If instead the slope
was linearly amplified to increase the slew rate at the desired trigger
voltage, then a much lower trigger jitter can be achived. Anyone
following the conversations of Bruce and myself should recognise this as
a reoccurring thing.
> This feels like the sort of thing that should have been hashed out here by
> now. Is it time to start a FAQ?
Bruce already has a bit of useful information, TvB certainly has, along
side of several other good members. Besides, folks here is very helpful
and eager to help a fellow time-nut. We also have archives.
> My straw man would be to capacitive couple into a 74AC00 that's biased
> halfway between VCC and GND. That's clean and simple. A transformer would
> break ground loops. A differential input chip might reduce jitter from noise
> on the power supply.
You can use self-biasing unbuffered CMOS inverters such as 4069UB as a
first stage amplifier and then use a few more in sequence to achieve
further gain. This trick have been used before and while certainly not
optimum it could be a useful little trick for simple single-chip
solutions where no major performance is expected. Hmm... I should
actually measure that one...
>> Feed it to a symmetrical divide by 2 for 5 Mhz, and a symmetrical
>> dive by 10 for 1 Mhz.
>> It seems the crowd is against 7490s, and 74390s - and I would like to
>> know what the crowd recommends as suitable.
> Dividing by 10 is simple. Doing it with symmetrical output takes a bit
> more/different logic than comes prepackaged in a single DIP, or at least not
> any that I'm familiar with.
> Plan A would use a 4 bit loadable counter and load it with 3 when it reads 12
> so the top bit would be off for 5 cycles, 3 through 7, then on for 5 cycles,
> 8 through 12. That's reasonable to implement in old TTL DIPs. 12 is easy to
> decode, just a 2 input gate since states 13-15 won't happen. 74xx163 and
The problem with the '90 is really that the output is not properly
synchronised. A half '74 solves that problem. The '90 is doing the
needed state-change, the '74 does the needed clock alignment.
> Plan B would be to use a PAL or CPLD. I don't know of any that are available
> in DIP, have free design software, and are easy to program without a fancy
> programmer. There could easily be something I don't know about. I know that
> Xilinx CPLDs have free software (WebPACK) but they don't come in DIP. A
> friend has written software to program them, but he's a wizard so I don't
> know if mortals could do it. WebPACK may do the programming if you have a
> gizmo. One is available at a reasonable price from Digilent.
> This technology is too handy. There is probably some hobbyist friendly setup
> out there. You may have to build a programmer.
The parallel port adapter is soooo easy. Infact you will find the
schematic of Xilinx dongle on their web. The JTAG variant is however not
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