[time-nuts] Frequency Divider

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Apr 3 11:01:49 UTC 2009


Ulrich

An open drain output buffer with a resistor pullup (and an drain voltage
rating of 5V or more ) would be ideal for the TDO level translator for
2.5V or 1.8V CPDs or FPGAs.
The open drain output could then be buffered by 1/4 74HC125 or similar
buffer with a 3.3V or 5V supply.

Bruce

Ulrich Bangert wrote:
> Bruce and Luis,
>
>   
>> Using a 74HC244 may be somewhat  problematic with CPLDs that 
>> don't have 5V tolerant inputs. Even when using a device with 
>> 5V tolerant inputs a 74HCT244 may be more suitable for 
>> translating LVCMOS logic level outputs from the CPLD.
>>     
>
> One chip that works very well for TDI/TMS/TCK translation from the printer
> port into the cpld is the 74AHC125 with its VCC connected to the cpld's VCC.
> This one can work with VCC as low as 2.0 V and is still 5 V tolerant on all
> inputs. At least with 3.3 cplds it's output swing is high enough for TDO
> back-translation. With 2.5 / 1.8 V cplds a separate TDO back-translation may
> become necessary.
>
> Best regards
> Ulrich  
>
>   
>> -----Ursprungliche Nachricht-----
>> Von: time-nuts-bounces at febo.com 
>> [mailto:time-nuts-bounces at febo.com] Im Auftrag von Bruce Griffiths
>> Gesendet: Donnerstag, 2. April 2009 23:38
>> An: Discussion of precise time and frequency measurement
>> Betreff: Re: [time-nuts] Frequency Divider
>>
>>
>> Luis Cupido wrote:
>>     
>>>   
>>>       
>>>> The CPLDs are programmed via the JTAG port.
>>>> Suitable JTAG programming cables are readily availble.
>>>>     
>>>>         
>>> Or you can build one to use the LPT port of your PC using just a 
>>> 74HC244.
>>>
>>>
>>> Luis Cupido.
>>> ct1dmk.
>>>
>>> _______________________________________________
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>>>
>>>   
>>>       
>> Luis
>>
>> Using a 74HC244 may be somewhat  problematic with CPLDs that 
>> don't have 5V tolerant inputs. Even when using a device with 
>> 5V tolerant inputs a 74HCT244 may be more suitable for 
>> translating LVCMOS logic level outputs from the CPLD.
>>
>> Bruce
>>
>> _______________________________________________
>> time-nuts mailing list -- time-nuts at febo.com
>> To unsubscribe, go to 
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>> and follow the instructions there.
>>     
>
>
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