[time-nuts] femtosecond jitter anyone?
Chris Mack / N1SKY
sometimesyoufeellikeanut at twentylogten.com
Thu Apr 9 02:03:29 UTC 2009
On Apr 8, 2009, at 8:50 PM, Bruce Griffiths wrote:
> If you divide the output down to ~38MHz using a noiseless divider then
> the performance is 20dB or more worse than can be achieved with a good
> ~38MHz crystal oscillator.
Ah, this would work, but there is a synchronization aspect since
framing on AES/EBU is in the mix (pun intended?) and there are more
pieces of external equipment that all need to be synched (within
AES11 framing sync margins)...
The box / design of interest has ADCs, DACs, and a 38.88MHz OCXO of
marginal performance coupled with the proposed DSP based PLLs
generating a local clock for the ADCs and DACs all on the same
circuit board in synch with external gear.
This 38.88MHz is a DSP clock, essentially a microprocessor clock
(albeit a very nice microprocessor clock) where the DSP simulates a
PLL operating on an incoming clock source, and makes an output clock
of a different frequency, but synchronized to be within AES standards
for framing when considering the additional equipment scattered
around the room, made by different manufacturers, different inner
The incoming clock source (master house clock) to this box / design
of interest is in another rack mount box external to this design on
the other side of the room and is anywhere from 44.1kHz up to a 10MHz
Rubidium (see also http://www.antelopeaudio.com). This clock source
on the other side of the room also drives other equipment to be in
synch for any framing on AES/EBU digital.
The output of the DSP PLL in this box / design of interest is 11MHz
to 24MHz to feed the oversample clocks on the ADCs and DACs,
synchronized to the external 44.1kHz to 10MHz master house clock a la
the PLL and the rest of the equipment on the other side of the room...
The only caveat is that the 38.88MHz DSP microprocessor clock must be
low jitter in order to have the DSP PLL be low jitter.. The DSP PLL
does not really care about absolute frequency in the long term
(38.88MHz or 37MHz, doesn't matter), but it will rebroadcast short
term effects of jitter to clocks of the ADCs and DACs in the box of
Sounds like maybe some LCs to filter out the additional harmonics and
maybe attempt to get close into the carrier eh?
Thanks Magnus and Bruce for being a sounding wall....
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