[time-nuts] femtosecond jitter anyone?
bruce.griffiths at xtra.co.nz
Thu Apr 9 03:53:49 UTC 2009
The biggest problem with the OCXO is probably that it has a square wave
With careful design it is possible to achieve a jitter of a few tens of
femtosec for a logic level output from a limiter, but the OCXO designers
are unlikely to have used such a limiter.
To produce a sinewave output, I'd probably start with a low Q (5? to
minimise phase shift tempco) tuned tank in the collector of a BJT driven
by a logic leve output to get an approximate sine wave and follow it
with an LC low pass filter with series tuned traps for the harmonics
across the shunt elements of the LC filter and adjust the filter
component values to achieve the desired response with the series tuned
LC circuits shunt elements in place.
Chris Mack / N1SKY wrote:
> Thanks Bruce,
> The 12kHz is a figure for the DSP PLL and how they measure it
> (starting at 12kHz usually for jitter over BW measurements).... I
> haven't touched SONET since 1997 and this may be a SONET spec?
> I am using the simulator software for the LMK04000 series to see what
> jitter is for the OXCO... -70dBc at 1 Hz, -100dBc 10Hz per the spec
> sheet with all the other datapoints comes out to 1.3ps (1Hz to
> 20MHz) of jitter RMS.
I presume the -70dBc @ 1Hz is a phase noise spec for the OCXO?
If so this is much higher than the state of the art for a sinewave
> So the OCXO is decent without having to purchase a better one (and
> the minimum quantity of 25 at $250 each +/-) for this initial
> prototype; this seems to be semi-custom since 38.88MHz OCXOs are not
> in stock at Digikey.... I plan on building a bunch of boxes over
> time with this OCXO in it and finding disparate OCXOs on ebay was not
> an option, especially if a new circuit board would need to be spun
> every time.
> I just didn't know if I could get better with some filtering, and get
> it into the femtosecond range... Currently this should be able to
> maintain 22 bits of accuracy at 40kHz, which is pretty doggone good,
> but was interested in pushing the envelope a little since I can go
> (with an input alias filter) to 96kHz... Yes, there is some internal
> jitter to the ADCs, some perhaps due to thermal, and the box is going
> to be hot with a power budget already at 250W hence the thermal /
> cooling and dither experiments and I was hoping to not be limited by
> the clock performance.
> I still want to filter such as to distribute a sine...
> On Apr 8, 2009, at 10:22 PM, Bruce Griffiths wrote:
>> Now we have a more complete picture of what you are trying to do our
>> suggestions will perhaps be a little more useful.
>> Cleaning up a marginal OCXO is quite complex and probably more
>> expensive than obtaining an OCXO or other reference that has lower
>> Is it in fact possible to just substitute a low noise non oven
>> oscillator for the 38.88MHz OCXO?
>> With an appropriate oscillator design it should be possible to
>> significantly reduce the phase noise of the 38.88MHz source at the
>> expense of long term drift and aging.
>> Achieving low jitter with such a source isn't difficult.
>> The other question that arises is why is the OCXO phase noise so
>> poor at
>> frequency offsets less than 12kHz?
>> Chris Mack / N1SKY wrote:
>>> On Apr 8, 2009, at 8:50 PM, Bruce Griffiths wrote:
>>>> If you divide the output down to ~38MHz using a noiseless divider
>>>> the performance is 20dB or more worse than can be achieved with a
>>>> ~38MHz crystal oscillator.
>>> Ah, this would work, but there is a synchronization aspect since
>>> framing on AES/EBU is in the mix (pun intended?) and there are more
>>> pieces of external equipment that all need to be synched (within
>>> AES11 framing sync margins)...
>>> The box / design of interest has ADCs, DACs, and a 38.88MHz OCXO of
>>> marginal performance coupled with the proposed DSP based PLLs
>>> generating a local clock for the ADCs and DACs all on the same
>>> circuit board in synch with external gear.
>>> This 38.88MHz is a DSP clock, essentially a microprocessor clock
>>> (albeit a very nice microprocessor clock) where the DSP simulates a
>>> PLL operating on an incoming clock source, and makes an output clock
>>> of a different frequency, but synchronized to be within AES standards
>>> for framing when considering the additional equipment scattered
>>> around the room, made by different manufacturers, different inner
>>> workings etc.
>>> The incoming clock source (master house clock) to this box / design
>>> of interest is in another rack mount box external to this design on
>>> the other side of the room and is anywhere from 44.1kHz up to a 10MHz
>>> Rubidium (see also http://www.antelopeaudio.com). This clock source
>>> on the other side of the room also drives other equipment to be in
>>> synch for any framing on AES/EBU digital.
>>> The output of the DSP PLL in this box / design of interest is 11MHz
>>> to 24MHz to feed the oversample clocks on the ADCs and DACs,
>>> synchronized to the external 44.1kHz to 10MHz master house clock a la
>>> the PLL and the rest of the equipment on the other side of the
>>> The only caveat is that the 38.88MHz DSP microprocessor clock must be
>>> low jitter in order to have the DSP PLL be low jitter.. The DSP PLL
>>> does not really care about absolute frequency in the long term
>>> (38.88MHz or 37MHz, doesn't matter), but it will rebroadcast short
>>> term effects of jitter to clocks of the ADCs and DACs in the box of
>>> Sounds like maybe some LCs to filter out the additional harmonics and
>>> maybe attempt to get close into the carrier eh?
>>> Thanks Magnus and Bruce for being a sounding wall....
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