[time-nuts] femtosecond jitter anyone?

[Bruce Griffiths]

Rick

The following NIST paper indicates that the conventional wisdom on ECL
phase noise levels appear to be incorrect at least for some ECL divider
configurations:

http://www.am1.us/Papers/U11605%20Low%20Noise%20Synthesis-%20Walls.pdf

Waveform symmetry and low power supply noise seem to be very important.

The output jitter of a a gate is dependent on its phase noise
properties, and the slew rate of its input signal at the threshold crossing.
Surely if the SiGe ECL devices were driven with an input with a
comparable slew rate surely its output jitter would be similar even for
lower frequency inut signals?

Bruce

Richard (Rick) Karlquist wrote:
> Bruce Griffiths wrote:
>
>   
>> Some ECL devices have jitter specs in the 100 to 200fsec range.
>> see:
>> http://www.onsemi.com
>>
>>     
>
> This is misleading.  While it is true that they have this
> low jitter at multi-Gb/s rates, the jitter is much greater
> than this at lower clock rates.  At 10 MHz, ECL devices
> can't do better than several ps random jitter.  This is
> because of the broadband phase noise floor which is around
> -150 dBc/Hz.
>
> Rick Karlquist N6RK
>
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