[time-nuts] time-nuts Digest, Vol 56, Issue 71

[Bruce Griffiths]

Tom

Tom Van Baak wrote:
>> Kit
>>
>> Probably the higher jitter and periodic phase modulation due to
>> simultaneous switching of multiple outputs at different frequencies.
>> The magnitude of the latter will depend on the loads driven by each output.
>>
>> The cure is to use an external flipflop to resynchronise the outputs to
>> the 10Mhz clock.
>>
>> Bruce
>>     
>
> Kit, Bruce,
>
> There was no phase modulation effect that I could measure.
> Note that in that design all pins (a single 8-but IO port) are
> re-written each time through the loop; not just ones that change.
> See the source code for details.
>
>   


But for example the 100KHz output pins actually only switch state every
5th cycle of the 1MHz output.
This will modulate the phase of the 1MHz output at 100KHz due to ground
bounce.
The magnitude of the modulation will depend on the load at the pins.
The higher the load capacitance (or lower the load resistance) the
greater the effect.
The effect will always be present, although whether you can detect it
depends on the resolution of the test setup and the pin load (C and R).
An SR620 is unlikely to have sufficient sensitivity for detecting the
effect with light pin loading.

In an FPGA with CMOS I/O such ground bounce and other coupling effects
can be a few tens of picosec even though the intrinsic jitter of the
internal logic elements is much smaller than this.
The PIC only has a single ground pin with a bonding wire inductance of a
few nH. If the outputs drive significant capacitance then the resultant
ground bounce can be significant.

An external flipflop can be connected so that it doesn't share the same
internal chip Vcc and GND wiring with outputs switching at different rates.
External ground plane noise can be much lower than internal chip GND net
noise.


> My understanding of the PIC architecture is that all outputs
> are essentially "resynchronized" to the clock by design. So
> that's why the PIC divider works so well. I can't see how an
> external off-chip flip-flop would be better than the existing
> internal on-chip flip-flop. Might even make things worse?
>
>   


Only if one uses a slower external flipflop and/or a poor clock
buffering scheme.


> But I don't know for sure and should not guess. In cases like
> this I'd take an actual test over a random guess.
>
> As for jitter, I tested the PIC divider when I wrote it ten years
> ago and if I recall correctly the jitter was just over what I could
> measure with a SR620; about 25 ps. With better equipment
> these days, one could measure how much of that is input jitter,
> or output jitter, or measurement system jitter. But I don't have
> anything better than a 5370 or 620 for 1PPS measurements.
>
> I know the PIC divider was an order of magnitude better than
> other discrete 1PPS dividers that I had at the time, and it was
> 100x better than the reference 1PPS out of any GPS boards
> that I had, so I was very pleased with the performance (and
> the simplicity, and the cost) of the one-chip divider concept.
>
>   


Almost anything reasonable is better than a cascade of 74XX90's with a
ripple cascade scheme between divide by 2 and divide by 5 sections.


> But it would be very interesting to me if someone with a working
> Wavecrest could make measurements of various PIC dividers
> and refine this old data; to find out just how low the noise floor is.
>
> /tvb
>
>
>
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>   

Bruce