[time-nuts] fast freq. synthesis schemes

Luis Cupido cupido at mail.ua.pt
Thu Oct 15 00:52:24 UTC 2009


Thank you all by your replies.
There are very good suggestions to investigate.

The solutions that a DDS is a reference of
large loop BW PLL may have indeed spurious issues
and is not so attractive.

The use of a DAC for coarse tune to get it
near lock is to be considered yes...
I'll detail a bit using to John's email
(makes it easier to address issues one by one)


 > Pretuning is the right strategy, but for microsecond agility,

Yes, I have always considered a DAC (as in my previous design)


 > YIGs may be the wrong choice due to their main-coil inductance.

No YIGs.
It is Hyperabrupt Varactor Tunned Oscillator
known as HTO's and yes it is full 12-18 and another model
for 8-12GHz


 > If I were building an agile 12-18 GHz synthesizer I'd try a heterodyne
 > scheme with varactor-tuned oscillators and a fixed
 > (or very coarsely tuned) YIG or DRO.
...
 > I would use a DDS, but only for fine tuning in a summing loop.
 >  E.g., use a
 > DAC to pretune the varactor or YTO to within 50 or so MHz,
 > feed the sampler
 > LO port with a clean 100 MHz crystal, then close the loop by
 > comparing the
 > sampler IF to the DDS-generated offset signal.
...

John, you described very closely the design I've implemented
quite sucessfully a few years back with just two minor
differences, I use the DDS as a reference
(not in a adding loop) and the coarse tunned LO is another simple
VCO and PLL in the 1-2GHz range with big steps (IF is about
250MHz and 100KHz step for a fixed 10MHz ref. and less than
1Hz resolution if the 10MHz ref came from a 100MHz DDS).

Works absolutely great but per design all was in the ms
switching time region, serial dac 2x serial PLL chips all in the same
3 wire bus and the 100KHz fcomp etc. Not easy to get any faster with 
simple changes.

Rescaling/redesigning the same concept into the microsecond
range is a lot of effort and I was thinking if a redesign
(including the lessons learned) would be the way to go or there was
some other clever schemes for the fast switching synthesizers.

I would hate myself if I start this design while missing a
much simpler approach.

That is the nearly the full story.

A lot more comments can come
and I will be happy an thankful.

Thanks.

Luis Cupido.
ct1dmk.




Hi John.

John Miles wrote:
> Pretuning is the right strategy, but for microsecond agility, YIGs may be
> the wrong choice due to their main-coil inductance.
> 
> If I were building an agile 12-18 GHz synthesizer I'd try a heterodyne
> scheme with varactor-tuned oscillators and a fixed (or very coarsely tuned)
> YIG or DRO.  Either way, you would probably use a sampler, such as the parts
> in the Aeroflex/Metelics catalog, to construct the outermost PLL.  Suitable
> counter and PFD chips exist as well (Hittite etc.) but samplers are cheaper
> and easier to use if you don't mind designing the IF circuitry for them.
> 
> I would use a DDS, but only for fine tuning in a summing loop.  E.g., use a
> DAC to pretune the varactor or YTO to within 50 or so MHz, feed the sampler
> LO port with a clean 100 MHz crystal, then close the loop by comparing the
> sampler IF to the DDS-generated offset signal.  That way the PN is dominated
> by the lower N factor assocaited with the 100 MHz comb, and the resolution
> is determined by the DDS.
> 
> -- john, KE5FX
> 
>> -----Original Message-----
>> From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com]On
>> Behalf Of Magnus Danielson
>> Sent: Wednesday, October 14, 2009 1:48 PM
>> To: Discussion of precise time and frequency measurement
>> Subject: Re: [time-nuts] fast freq. synthesis schemes
>>
>>
>> Bob Camp wrote:
>>> Hi
>>>
>>> At least on paper you can run a DDS at VHF/UHF and put it into a (very)
>>> wideband PLL driving a 12-18 GHz VCO.
>>>
>>> As mentioned previously - spurs will be an issue. You also will
>> need to get
>>> a hold of some DDS chips with GHz-ish clock rates.
>> One could use a suitably high frequency VCO or even YIG, locked to a DDS
>> and then use a suitable fixed oscillator for up-conversion. The PLL
>> locking would also use a DAC for VCO "bias" being updated at the same
>> time as the DDS. A look-up-table could be used for top DDS frequency to
>> bias conversion and a calibration round could be used to trim the table
>> up to minimize the bias-error. That way the VCO can be quick-jumped and
>> the PLL will immediatly steer the frequency back into lock. The PLL loop
>> thus only needs to handle error in bias-table, the remaining difference
>> in frequency and phase-relationship. Quite a different task than the
>> overall lock-range. An ADC for the non-biased value of the loop-filtered
>> detector would enable calibrations to be made automatic.
>>
>> Cheers,
>> Magnus
>>
>> _______________________________________________
>> time-nuts mailing list -- time-nuts at febo.com
>> To unsubscribe, go to
>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>> and follow the instructions there.
>>
> 
> 
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
> 



More information about the time-nuts mailing list