[time-nuts] OT: Practical PLL low noise?
lists at cq.nu
Tue Feb 2 18:15:08 UTC 2010
I happen to like the Analog Devices ADF4001 for this sort of thing. You
would need two of them, one for each oscillator. The National chip
mentioned earlier will also work. The 2306 it's self is obsolete, but I'm
sure there are other National parts that will drop into the same socket.
Either way you will need something like a PIC to "shoot" the settings into
the chip. It looks like all that is taken care of on the board in the
earlier post. The code on the PIC would need to be re-written to match up
with what ever chip you decide to use.
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of francesco messineo
Sent: Tuesday, February 02, 2010 12:58 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] OT: Practical PLL low noise?
On 2/2/10, Bob Camp <lists at cq.nu> wrote:
> The first issue - your oscillator may be drifting quite a lot. If so,
> the first thing to check and possibly fix. A reasonable oscillator should
> able to hold less than 100 Hz at 42 MHz under normal room conditions.
> range from circuit improvements, to a better crystal, to simply
> a draft that blows on the oscillator.
it is drifting about 50 Hz during warm up, but the problem is thermal
drift internally as season changes, as tx/rx periods change, and so
> If the oscillator is reasonably stable, it will need to be turned into a
> VCXO in order to lock it. If both oscillators use fundamental crystals,
> should not be very hard. If they use higher overtone crystals it may be
> of a challenge. Often you will find a tradeoff between good oscillator
> performance and wide tuning range.
22 MHz can be fundamental, 42 MHz is third overtone for sure.
> What ever chip you use to do the lock, keep the loop bandwidth small. The
> GPSDO will be noisy and it will not help you for phase noise. I would
> the bandwidth at 100 Hz to be sure everything works ok and then start
> narrowing it to 10 Hz or less. At some point the loop will be to narrow
> "keep up" with the changes and you will not be able to maintain phase
> What ever loop bandwidth you use, keep the phase margin large. You do not
> need a fast locking loop. Instead you need one that has less tendency to
> peak. Phase margins should be above 70 degrees.
> The nice thing about doing this with a chip is that most of the
> manufacturers have cute little web applications / free downloads to
> the loop filters for you. No digging out crazy formulas and wondering if
> got it all right.
thanks for the suggestions, any good candidate as a chip?
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