[time-nuts] Updated Shera controller
lists at rtty.us
Fri Jul 30 21:09:37 UTC 2010
There's a couple ways to do this:
One is to actually measure the 1:1000 or 1:4000 voltage settling involved.
That's tough on most scopes. You can set up to do it if your TEK 7000 plug
in collection is large enough.
The other is to look at the observed time constants and come up with a
number for "one tau = xxx ns". From that point it's simply a math exercise
to get to how ever many bits.
In the real world, neither one is perfect.
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Richard H McCorkle
Sent: Friday, July 30, 2010 4:54 PM
To: time-nuts at febo.com
Subject: Re: [time-nuts] Updated Shera controller
To confirm the buffer settling time measurements were made on
two cascaded TS272 2x gain stages on a solderless breadboard
using 10k resistors on first stage and 100k resistors with 2.5v
offset correction on second stage similar to the PICTIC II
buffer arrangement. The input was stepped using a 50 KHz logic
waveform thru a divider to vary the input level. A two channel
scope was triggered by the input rising edge and the delay to
the output peak and final settled voltage from the second
buffer was measured at 500ns/div.
In all cases there was a delay before the waveform began to
rise, a peak with a small overshoot, and 500ns later the output
voltage had stabilized. The pulse amplitude was varied over a
1.7v to 2.7v range similar to the data voltage range used in
the PICTIC II. The delay to peak varied from 1.7us to 2.4us
with larger input voltages requiring longer times to peak. In
all cases the voltage settled to its final value within 500ns
after the waveform peak, so worst case the buffer output was
stable 2.9us after the input leading edge. The 16F688 spec
sheet recommends a maximum input impedance of 10k ohms so the
buffer is required. It also recommends 4.7us between ADC
channel select and conversion start to charge the channel
input capacitance and combined with the interrupt overhead it
takes approximately 10us to start the ADC read.
>You can't predict the settling time of an opamp from its slew rate or
its gain-bandwidth product.
>The TS272 datasheet has no settling time spec whatsoever.
>In this case, since there is no spec it needs to be measured.
>Opamps with 2 or more cascaded gain stages like these are notorious for
poor settling times.
>10us is merely guesswork.
>The settling time could well be much longer and it may depend on the
input signal level.
>Richard H McCorkle wrote:
>> The TS272/TS274 have a slew rate of 5.5v/us at unity gain, the max
>> voltage on the cap is 2.7v in the new design, and the voltage is read
>> > 10us after sample complete, so the buffer should have time to
>> stabilize after the sample before being read.
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