[time-nuts] Help with TCXO
attila at kinali.ch
Tue Dec 6 22:04:49 UTC 2011
On Tue, 6 Dec 2011 21:47:24 +0100
Azelio Boriani <azelio.boriani at screen.it> wrote:
> I have read about the two main delay line techniques: the vernier delay
> line and the tapped delay line. These require a sort of on-the-fly
> calibration virtually for every sample you get because of the temperature
> and power supply dependency of the delay itself. Presently my
> time-to-digital converter has a 2.5nS resolution made only by counters,
> based on a 100MHz clock and on the capabilities of the Digital Clock
> Manager in the Spartan3 XC3S50 FPGA. In your opinion what resolution can I
> get from a Spartan3 (without any calibration) using delay lines? I have to
> learn how to manage delay lines and how to direct their placement for
> time-nut purposes.
Google for . Wu et al reports that he was able to get to <60ps RMS
uncalibrated on a Cyclone II chip (which is quite old and slow).
Calibrated it was in the range of 10-25ps RMS (depending on the
In  Qi et al "verify" the result from  and get to 20ps RMS with
30ps RMS worst case. Unfortunately, they don't write which FPGA they used.
(At least i couldnt find it just now)
 The lO-ps Wave Union TDC: Improving FPGA TDC Resolution
beyond Its Cell Delay, Jinyuan Wu and Zonghan Shi,
2008 IEEE Nuclear Science Symposium Conference
 A 20ps Resolution Wave Union FPGA TDC with On-Chip Real
Time Correction, Ji Qi, Zhi Deng, Hui Gong, Yinong Liu
Why does it take years to find the answers to
the questions one should have asked long ago?
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