[time-nuts] 10MHz to 80MHz frequency multiplier suggestions
dk4xp at arcor.de
Tue Feb 1 09:30:25 UTC 2011
Am 31.01.2011 22:48, schrieb dave powis:
> Hi Chris,
> Yes, of course the multiplication plan is a little different, but in
> the circuit
> I linked the basic multiplier is a doubler from 10 to 20MHz, that
> produces a
> comb of 2f products. The design as presented has BPF's to select the 5th
> harmonic, and I was simply suggesting that by replacing these with
> 80MHz BPF's
> the same simple circuit would also be useful for the other respondent
> who wanted
> that frequency rather than 100MHz. As Rick has subsequently suggested, 3
> cascaded doublers would achieve the 80MHz requirement very well, but
> of course
> they will not solve the 100MHz problem. For 100MHz you can easily do
> it in two
> diode multipliers - one to 50MHz (x5) and a doubler to 100MHz. But
> that's now
> two diffferent circuits, and I was looking at the $10 option..
I don't like this frequency multiplying idea. I've just tried a
10->5->35 MHz multiplier
for a DG8SAQ VNWA and the filtering was much more work than anticipated.
(and 10-> 30 MHZ....etc) .
-60 dB is nothing in a SDR with a dynamic range approaching 100 dB.
By carefully multiplying a state-of-the-art 10 MHz source,
you can be better by some dB close to the carrier, but far off you loose
* 10 in frequency will cost 20 dB in noise floor, probably more. So from
-178 dBm/sqrt Hz
you are _UP_ to -158. That's not bad, but nothing to write home about.
The best thing to do is a 80 or 100 MHz crystal VCXO . This will give
you an acceptable
noise floor. If You lock to a quality 10 MHz source, you can transfer
the low close-to-
the-carrier phase noise of the source to the 100 MHz osc, as far as it's
in the pll bandwidth.
But that means quite an effort and may not be worth it if you have a decent
100 MHz VCXO. In fact, one can easily mess it up without the right tools.
(signal source analyzer...) For starters, I would lock the 100 MHz with
a low bandwidth
loop to the 10 MHz.
No 10 MHz-harmonics in the output and no filter tuning nightmare...
Harmonics of the 100 MHz don't care, you may have to square it up for
the ADC anyway.
> I'm well aware that time nuts is probably the very worst reflector on
> which to
> post a 'simple' solution! However, it was, as I thought I had made
> clear, my thoughts for the $10 solution - I fully accept Bruces'
> comments about
> the ACMOS jitter issues, and as always it is up to the user to do his own
> homework as to suitability.
There is no fundamental law that makes ACMOS look bad. In fact, your
LTC2208 or whatever ADC is low voltage CMOS, too.
The diagram in (1) shows FAST and AC dividers at <150 db/sqrt Hz
at 10 Hz offset. I would like to see an osc at 100 Mhz or multiplied 10 MHz
that can do that.
> I'm also aware that it is very easy to become
> 'over-focussed' on specs, and forget what the original job was to do!
> neither respondent was specific about what they are trying to measure
> or receive
> with their SDR's, or the ADC to be used, no-one can give meaningful
> but there are many who can tell you the best way to do it!
> I'm coming from the position that Robert Watson-Watt, of UK radar
> fame, held - of course everyone wants the best, but that will take
> expensive. They would be very happy, and probably not tell the
> difference from
> that if given the second-best solution - so he aimed to deliver the
> solution as a starter, and work towards second-best, on the basis that
> would have 'something operational' in the shortest time.
73, Gerhard, DK4XP
(1) James A. Crawford, Frequency Synthesizer Design Handbook, Artech
House, pg. 81
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