[time-nuts] Frequency multiplication
armstrong at sedsystems.ca
Wed Feb 2 19:17:12 UTC 2011
FPGA's do not have good jitter performance. Both Altera and Xilinx have
app notes and specs on what to expect for jitter performance.
Particularly when using high speed DACs (like the ADI AD9739) the
technique used is to drive the DAC with a good quality clock, then the
DAC drives the FPGA. With high speed dac's like this there is often a
DLL used to optimize the data edges with respect to the clock.
Similar techniques are used in the other direction ADC ._ FPGA. The
good clock is given to the DAC which presents the clock to the FPGA.
The clock out of an FPGA may be good enough depending on what you are
using it for but check carefully!
On Wed, 2011-02-02 at 10:47 -0800, Hal Murray wrote:
> > Bottom line - there's a lot to look into, and they are unlikely to help you
> > out.
> There are a lot of FPGAs used in DSP applications where the clock to the
> front end ADC is critical. So I'd expect there would be some in-house
> knowledge about this area. It may be that all the help you will get is
> "Don't do that."
> I think Altera uses PLLs.
> Xilinx uses DLLs, D for delay, a long chain of gates with an adjustable tap.
> So the output signal will jump in time when the tap switches.
> FPGAs are designed for digital logic rather than clock hacking. I remember
> some story from years ago about clocking troubles being traced back to input
> threshold changes due to nearby outputs switching. I forget the details. I
> think that particular problem was solved by moving all the output pins away
> from the clock input pin.
> The smaller FPGAs are not expensive. It might make sense to dedicate a whole
> chip to something like a clock mux.
> You could always use an external PLL and put the digital dividers in a FPGA.
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