[time-nuts] Fwd: 10MHz to 80MHz frequency multiplier suggestions
vu2zap at gmail.com
Thu Feb 3 07:02:55 UTC 2011
My object of the exercise was to multiply the error of a 10Mhz Rb /GPSDO source
so that I would get 8x phase error between two compared frequencies.
This I presume would make adjustments of my sources much easier.
OTOH, if we lock 80Mhz to Rb source and use that as a clock for the Super
DDS 2 VFO kit, then I would have a pretty good HF signal source.
>our ULN-1100 and ULN-2550 GPSDO's use a 100MHz VCXO locked to the 10MHz
>OCXO via an ADF4002 PLL with less than 40Hz bandwidth. After careful
>optimization of the layout and the loop filter, the phase noise results are quite
>excellent at 100MHz, see the attached plot. The plot shows two versions of
>the PLL loop filter from the design phase of the products, one has been more
>optimized. You can see that the noise floor is almost -170dBc/Hz at 100MHz.
>You get the best of two worlds: the absolute frequency accuracy of the
>GPSDO, and the very low phase noise of the VCXO above the PLL bandwidth. It is
>clearly visible that the VCXO phase noise inside the loop bandwidth is
>actually also reduced by locking it to the 10MHz OCXO (the PN curve below the
>loop bandwidth frequency of ~30Hz would just continue going up without the
>Low Noise 100MHz VCXO's are readily available at mouser and digikey (so
>are 80MHz units), and programming the ADF4002 is straight forward with the
>help from the AD online tools. It can be bit-banged with any microcontroller.
>I was contemplating the same thing. I fed the output to a bifilar
>diode doubler and got good results. I have to add an amp and double it
>more. It is still on breadboard. The object was to multiply the error 8x
>Probably a PLL locking to 80 Mhz will retain the long term accuracy of the
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