[time-nuts] TEC party file format?
Tom Van Baak
tvb at LeapSecond.com
Wed Jun 29 19:14:48 UTC 2011
> I suspect all of this happens MUCH faster then you could implement
> using 7400 series TTL logic. The 5ns gate delay of a TTL chip is an
> "eternity" for a modern CPU. Even for me who works with computers
We may be getting OT, but this assertion can't be true. If you
factor in all the things that affect latency in an intel cpu and
modern operating system, you'll appreciate why.
Instructions have to be fetched. You may or may not get cache
hits. There are multiple levels of cache. Multiple cores vying for
locks at multiple levels of cache and memory. Virtual addresses
need to be translated. Page tables. TLB misses. Data cache hits
and misses. DRAM refresh. Instructions executed out of order.
spin locks. cpu interrupts. bios interrupts. os interrupts. paging.
swapping. The list goes on.
True, things may happen at the sub-nanosecond inside a GHz
intel cpu, but the one thing 7400 chips (and microcontrollers)
have going for them is determinism (low jitter).
If you need both sub-ns and low jitter, then use a TIC (hp 5370,
SR 620, hp 53132, PICTIC, etc.).
Out of curiosity, if anyone on the list has pointer to papers that
show actual measurements of desktop systems used as precise
timing devices let me know. Not external boxes or PCI cards, but
using the OS itself as a timer. I'm sure with care 1 us or even
100 ns is possible. For example, how accurate is the best NTP
system? But this is still a thousand times more jitter than plain
logic circuits and a million times worse than specialized TIC's.
Reply off-line, I know this is getting very off-topic.
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