[time-nuts] 50/60 Hz clocks, start at 60M0 Hz
semiflex at comcast.net
Wed Mar 23 20:29:52 UTC 2011
Just thinking here about making a 60M0 Hz oscillator and
phase locking it to the 10M0 reference. Then divide the
60M0 by 1e6. Youve got a perfectly locked 60 Hz square
For low harmonic 60 Hz sine wave one can go for 480 Hz
to start a Walsh -Hadamard converter. Take 60M0 divide
by 125 (easy with a binary counter) then divide by 1000.
Result is 480 Hz. Take the 480 Hz and build the output
stage with a DG201 CMOS switches (or similar) and
a couple of opamps. Result is very low harmonic perfectly
locked 60 Hz signal ready to drive an audio amplifier.
On 3/23/2011 1:03 PM, Magnus Danielson wrote:
> On 03/22/2011 11:45 PM, Hal Murray wrote:
>> magnus at rubidium.dyndns.org said:
>>> On the other hand, it would not be difficult to make a DDS which
>>> hit 60/
>>> 10000000 exactly. Reducing it by 20 on each side you get 3/500000
>>> so a 19
>>> bit accumulator (mod 500000) incrementing with 3 on every 100 ns
>>> would do it.
>> Neat. Thanks.
>> I'd noticed that adding in decimal rather than binary would make
>> exact target
>> frequencies in some cases, but I hadn't generalized to adding modulo N.
>> Using N of 10,000,000 with a 10 MHz clock gets you all exact integer
>> frequencies in the audio range.
> Which was my main point... it doesn't have to be THAT complex. A
> 500000 entry LUT is however expensive.
>>> A LUT for sine would be possible. Playing a few tricks with the LUT
>>> (realizing that the LUT would be walked through three times with three
>>> different start-alignments) converts it into a LUT of the same size
>>> and a
>>> increment by one or decrement by one counter modulus 500000. A
>>> decrement by
>>> one counter allows wrap-around loading with 499999 easy. CPLD or
>>> implementations would be trivial for the counter. The LUT will be
>> More neat. Thanks again. It's just a simple state machine cycling
>> some collection of states.
> Exactly. It really helps when trying to understand spurious response.
> A DDS has a large number of states and for most frequencies, all
> states will be visited before looping. A 32-bit DDS clocked at 10 MHz
> wraps in 429.4967296 s. Half the possible settings will wrap quicker
> (at various power of 2 variants).
>> If we are willing to rearrange the LUT/ROM, we can simplify the next
>> calculation from a modulo adder to a re-loadable counter.
> Which is what I propose above.
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