[time-nuts] FE 5680A "new version" - Filtering the 10 MHz
beale at bealecorner.com
Wed Nov 16 00:25:36 UTC 2011
Sylvain Munaut wrote:
> It's not generated from a DDS. It's from a xilinx PLD, then through an L and then through a C to the RF connector.
> The signal at the L output is fairly sinusoidal (at least monotonic near the crossing), but after the cap, it's like that ...
While I'm waiting for my own FE-5680A to arrive... that "sine" wave certainly looks awful. What kind of signal is coming from the Xilinx PLD pin, before the L? Is it a simple 10 MHz square wave, or some kind of >> 10MHz PWM intended to approximate a 10 MHz sine wave?
If it is a 10 MHz square wave, can I use that as a 10 MHz clock directly (probably through a digital buffer) or does it have a lot of jitter, which the LC filter was supposed to smooth out?
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