[time-nuts] PICTIC II ready-made?
davidwhess at gmail.com
Thu Apr 26 03:54:14 UTC 2012
Their technology paper talks a lot about differential inputs and
outputs but their 74G series is naturally all single ended. They also
discuss using multiple bond wires to reduce inductance so maybe that
was all that was needed.
They sell through an Ebay store but given the price of $3 per chip and
$2 for shipping and handling, I would be inclined to design with
readily available ECL which is not much more expensive.
On Wed, 25 Apr 2012 19:17:43 -0300, Daniel Mendes <dmendesf at gmail.com>
>About replacing the 74ACT175... there´s a company called "Potato Semi"
>(well.. they make "chips", right?) whose sole business is to make damn
>fast 74 logic. Their chips can be bought at ebay in small quantities.
>Look at this 600MHz D flip flop:
>Em 25/04/2012 16:15, Bruce Griffiths escreveu:
>> Chris Albertson wrote:
>>> On Wed, Apr 25, 2012 at 9:37 AM, Don Latham<djl at montana.com> wrote:
>>>> I forgot to add that a simple redrafting of the II as an Arduino shield
>>>> with appropriate chips and chip passives would accomplish the desired
>>>> end without losing the very careful engineering and testing that has
>>>> already been done?
>>>> Would be nice to have a way to change caps without soldering as well,
>>>> maybe just some .1" jumpers?
>>> Yes, MOST of the design could be re-used. As an Arduino shield there
>>> is no
>>> need for a PIC or RS-232 interface becusethe Arduino does that function.
>>> You'd need to replace the 74ACT175 part but that is not hard.
>>> About changing the cap values without soldering. I guess you could push
>>> the leads into a 0.1 inch header strip or install several and use a DIP
>>> switch to select which are "in". But I don't know if the extra
>>> al that wiring adds is enough to worry about.
>> The time to digital converter (TDC) section is merely an interpolator
>> that measures the delay of a synchroniser.
>> The TDC range should be about 2 clock periods to accommodate the range
>> of synchroniser delays and to facilitate calibration.
>> Unless one is changing the synchroniser clock period there is no need
>> to vary the TDC gain.
>> The SR620 uses a similar interpolator and has only a single
>> interpolator range.
>> The range is extended by counting the number of synchroniser clock
>> periods between synchroniser output transitions of interest.
>> When measuring the time interval between 2 signals a pair of
>> synchronisers and interpolators are used.
>> Interpolator nonlinearity can be measured by using a statistical fill
>> the buckets technique which uses nothing but a pair of noisy
>> asynchronous oscillators with high reverse isolation to avoid
>> injection locking.
>> If a suitable ADC is used the interpolator can be simplified
>> considerably whilst improving its performance.
>> Minor nonlinearities are of little significance, as long as they are
>> repeatable and relatively stable they can be easily corrected in
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