[time-nuts] ANFSCD - Synchronizing time in home video recorders
azelio.boriani at screen.it
Fri Feb 3 09:16:26 UTC 2012
Yes, DLL not DDL I made a mistake. Actually it is not in my schedule to
make such a divisor, just for speculation. The main thought here is that,
as you pointed out, it can be done avoiding PLL and DLL.
On Fri, Feb 3, 2012 at 1:49 AM, Hal Murray <hmurray at megapathdsl.net> wrote:
> > OK for the PSOC example. At the moment I can try on a Spartan3 because I
> > already have a board with the OCXO. The Spartan3 has the so called DCM, a
> > digital clock generator that can multiply an input clock using its DDL
> > digital delay line.
> The original context was keeping wall clock time. In that application,
> jitter on the 32 KHz clock isn't a problem.
> If I was hacking with a FPGA, I'd make a decimal addition module and chain
> of them together and see how fast it goes. The idea is to avoid the DLLs,
> If it runs at 10 MHz (100 ns), I'd declare victory and try to see how well
> works. I'd probably divide by 32K and compare that with another handy PPS.
> If it doesn't run at 100 ns, I'd probably insert a pipeline FF in the carry
> chain, or as many as were needed. It won't change the overall result, just
> delay the output signal by a clock cycle.
> If that worked, I might try to see how fast I could get it to run. That's
> just for fun/ego. The obvious target is 100 MHz which just adds one more
> decimal counter stage and probably several/many pipeline FFs. That should
> cut the jitter from 100 ns peak-peak to 10 ns. It won't change the overall
> frequency stability.
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