[time-nuts] Rubidium Performance: DDS noise effect on 10 MHz
jmiles at pop.net
Sat Feb 4 08:17:46 UTC 2012
> In the current 5680A units, the 10 MHz output comes from the 60 MHz VCXO
> (divided by 6 in CPLD) and not direct from a DDS. If my architecture
> understanding is right, the DDS signal output is mixed with the VCXO
> only at the 114th harmonic of 60 MHz, and it's the PLL (looking at the
> signal from the Rb) that drives the VCXO to keep it lined up. As I
> it, DDS phase noise should be divided by a factor of 6*114 by the time it
> appears at the 10 MHz output, and at larger frequency offsets the
> should also be (significantly) reduced by the PLL loop filter.
> I don't have any phase noise measurement tools myself, so this is just an
> academic argument, but if there is significantly more noise on the 10 MHz
> than expected for a 60 MHz VCXO, I wonder if it's just inadequate
> an internal power rail. Is the unit under test being driven by a linear,
> switching supply?
What made me suspect the AD9832 is that the PN/spur behavior is so close to
what I'd expect from it. Analog Devices' own plots contain a lot of strong
spurs, and the chip's actual SFDR spec is in the -70 dBc range that I'm
seeing (blue trace attached). But yes, you're right, it would make a lot
more sense to use the DDS as an offset generator for the control loop,
rather than as an output device.
I tried it with a couple of different supplies, linear and otherwise, and
the noise didn't change meaningfully. Since it's so far out of line with
FEI's specs, I have to believe that I either got a couple of bad examples --
although they lock very quickly and look essentially unused inside -- or I
don't have the pinout right, and am using the wrong ground or something like
that. Seems pretty unlikely that this is normal operation. Let's see what
JohnA comes up with.
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