[time-nuts] GPS / GNSS front-end board
azelio.boriani at screen.it
Sat Jun 9 11:42:12 UTC 2012
And try to put the unused I/O pins to GND too. Xilinx suggests, to reduce
noise, to ground the FPGA using as more free I/O pins as possible and
configure them as low logic level. Of course this trick does apply to other
On Sat, Jun 9, 2012 at 6:54 AM, Hal Murray <hmurray at megapathdsl.net> wrote:
> > * Connect all free pins of the FPGA to a 2.54mm header pin connector
> Don't go overboard on the "all" if that makes a mess of the routing or
> Be sure to put "enough" ground pins on the header(s). Power too.
> These are my opinions. I hate spam.
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