[time-nuts] WWVB BPSK Receiver Project?
lists at rtty.us
Thu Mar 15 16:42:55 UTC 2012
If you can handle the data rates for Loran at 100 KHz with a micro, then you
should be able to handle the data rates for something at 60 KHz. My guess is
that a simple "I know what the waveform is now compare it" approach would
not be terribly processor intensive. Put another way, you can easily predict
exactly what the signal will be doing at any instant. You just need to steer
to the error from that prediction.
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Attila Kinali
Sent: Thursday, March 15, 2012 10:26 AM
To: shalimr9 at gmail.com; Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] WWVB BPSK Receiver Project?
On Thu, 15 Mar 2012 13:50:08 +0000
shalimr9 at gmail.com wrote:
> Do you need 16 bits or can you get by with a 12 bit ADC?
> Have you considered using an FPGA for signal processing? It seems you need
a fairly serious CPU to handle that much data.
I think Poul-Henning is refering to his AducLoran receiver, which
used a 1Msps ADC . I dont remember what he exactly does with the signal,
but IIRC he uses a 40MHz uC which leaves him with 40 Cycles per sample,
which is quite a lot if you only do just some math calculation to detect
the start of a second...
And unlike with the FPGA, it does not take more time to process 8bit
or 24 bit samples as the uC works with 32bit numbers anyways.
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin
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