# Spectracom 8164 EFC Analysis

The 10MHZ oven-controlled oscillator in my Spectracom 8164 was intermittent, so I decided to replace it with an HP 10544A oscillator, which is a quite good standard (though it's not quite as good as the more modern 10811 series). This page has some information about how the 8164 steers the oscillator via its microprocessor and digital-to-analog converter. Mainly, it's about how to make the HP oscillator, which has different EFC tuning specs than the original, work properly.

At least, that was my plan when I started. As you'll read below, it turns
out that the stability of the received WWVB signal is the main limitation
on the unit's frequency stability, and to make a long story short, it's
not worth spending a lot of time tuning the oscillator tuning performance.
Without changing the unit's firmware (and the source code isn't
available), there's not much you can do on the hardware front to improve
the performance beyond the 1x10^{-9} level.

## How the 8164 Works

The 8164 uses a frequency-lock-loop to control the frequency of the internal standard in terms of WWVB. To do this, a second 10MHz oscillator is tightly phase locked to the WWVB signal and is used to gate a frequency counter that monitors the higher-quality internal standard.
Although the WWVB signal as received has quite a bit of short term jitter,
the gate time is 1000 seconds, and that's long enough (in theory) to
average out this noise. The 1000 second gate time allows the counter
circuit to read with a resolution of 1x10^{-10}.

**First important fact:** To further protect against errors from short
term propagation effects, the CPU makes an adjustment only when three of
the last four 1000 second counts agree to within 1x10^{-9}.

I'm pretty sure that the adjustment is a purely linear one with no compensation near the edges of the range, and no "learning" to proactively compensate for the standard's aging. The unit simply measures how far off frequency the oscillator is, and applies an adjustment to the frequency standard's electronic frequency control ("EFC") input to bring the frequency as close as possible to the nominal 10MHz.

**Second important fact:** The algorithm appears to make an adjustment
only if the average error of the three readings is 3x10^{-10} or more.

The original oscillator had an EFC tuning range of 10Hz, and this adjustment occurred over a tuning voltage range of +2.5 to +5 volts. The digital-to- analog converter ("DAC") used to generate the control voltage has 12 bits of resolution, or 4096 discrete steps.

**Third important fact:** The system is designed so that a one-step
adjustment to the DAC will change the oscillator frequency
2.44x10^{-10}. Based on a ~2.5 volt control range, the original
oscillator had a tuning sensitivity of about 0.00061V/step, or 4.0Hz/volt.

## Interfacing to the HP 10544A Oscillator

The HP oscillator has a tuning sensitivity (frequency shift per volt of EFC) of about one-tenth that of the original oscillator. If I just plugged it in without making any other changes, the Spectracom's DAC adjustments would only have 1/10 the impact they should, and as a result the frequency would reach the correct value only very slowly.
**Fourth important fact:** The HP 10544A has a rated EFC range of
+/- 1Hz over a +/- 5V range -- or 0.2Hz/volt. Here's a graph of the tuning
range I measured:

If we look at the most linear part of the curve, the frequency change over the 10 volt range between -7 to +3 volts is about 1.3Hz, or 0.13Hz/volt.

The CPU thinks that one DAC step is equal to 0.002441Hz. The next step is to figure out what V/step is required to achieve that over the linear range of the HP oscillator's EFC input. Extrapolating from the graph above, it takes 8.5V to move the oscillator 1Hz. That's ten percent of the range the DAC thinks it's controlling, so the DAC needs to move 8.5V over ten percent of its range, or 410 steps. 8.5V/410 is 0.020731 V/step, and that's what we need to come up with as the ultimate DAC output.

It looks like the original DAC circuitry could be adjusted to provide up to about a 10 volt range, which can be made either positive or negative (but with the original circuit is unipolar -- the range can't span 0V). 10 volts over 4096 steps is 0.00244V/step.

I've spent a fair bit of time messing with the DAC output circuit. I redesigned the output to match the bipolar design shown in the National DAC1208/../DAC1230 data sheet (page 13) with the input resistor set to 10k. This allows the output to swing from +|Ref| to -|Ref|, with 0V in the middle. That effectively doubles the output voltage range (and thus the maximum Hz/step) from what the original circuit could do.

With a reference voltage of +6.0, the output swing from a DAC setting of 000 to FFF is 13.23 volts, from -5.94V at 000 to +7.29V at FFF. That calculates to 0.0032V/step across the range. The output is very linear; the volt/step ratio remains within .1mv of this value when looking at the central 25% of the range.

To operate the 10544A in the most linear part of its EFC range, the control voltage should be around -3V when on frequency. That means setting things so the DAC is at about 300 or slightly lower when locked to frequency.

## Some Data

I've been running the 8164 for several days now, with the DAC output set to provide the maximum volts/step that I can get without wiring in a hardware amplifier.The plot reflects the frequency error of the oscillator as well as noise on the WWVB signal. We'd expect to see a slope at first while the oscillator is steered to frequency, followed by a fairly flat line showing the noise on the WWVB signal as well as any step adjustments the CPU makes to steer the oscillator. The plot begins at about 4:00PM on December 14, so there's more night than daytime propagation represented.

You can see the frequency steps at the beginning while the unit steers
toward the correct frequency. After that, the main thing to notice is
that while the slope of the line is flat, there are signicant excursions,
typically from one extreme to the other on subsequent counts. There are a
few significant spikes of 80 - 100 parts in 10^{10}, but there's
also a recurring pattern of one data point that's 20 or 30 parts high,
immediately followed by one that is about the same amount low (or the
reverse). It appears that this results when the transition between 1000

Here is a plot of the DAC readings during this same period:

Here is the DAC plot with the scale expanded to make the steady-state steering action more visible. The steep curve at the beginning of the run is clipped off the top of the chart.

## Hex-to-Decimal Frequency Conversion

Frequency |
10 Sec. Gate |
1000 Sec. Gate |
Comment |

10 000 002 500 | 0000 05F5 E119 | 0002 540B EDC4 | DAC-ZERO |

10 000 000 100 | 0000 05F5 E101 | 0002 540B E464 | |

10 000 000 050 | 0000 05F5 E100 | 0002 540B E432 | |

10 000 000 010 | 0000 05F5 E100 | 0002 540B E40A | |

10 000 000 000 | 0000 05F5 E100 | 0002 540B E400 | Nominal |

9 999 999 990 | 0000 05F5 E100 | 0002 540B E3F6 | |

9 999 999 950 | 0000 05F5 E100 | 0002 540B E3CE | |

9 999 999 900 | 0000 05F5 E0FF | 0002 540B E39C | |

9 999 992 500 | 0000 05F5 E0B5 | 0002 540B C6B4 | DAC-ONE |