[time-nuts] Interfacing a 8dBm sine output of an OCXO to a
digital logic standard
Poul-Henning Kamp
phk at phk.freebsd.dk
Fri Sep 16 10:43:26 EDT 2005
In message <a06230901bf5081d351a4@[192.168.0.8]>, David Forbes writes:
>>My very stable OCXO output a 8dBm (50ohm) sine wave. How is this signal
>>converted/interfaced to a logic standard (e.g. LVDS)?
The best way to do it is actually with 1:1 PLL.
In modern computers the synchronous RAM requires clock signals which
have very tight specs on delay and jitter and the only way this is
possible in practice is by using 1:1 PLL's as "zero delay buffers".
See for instance:
http://www.icst.com/datasheets/ics2305.pdf
ICS has many interesting clock chips which can be used for other
uses than what they were designed. Worth a browse.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
More information about the time-nuts
mailing list