[time-nuts] More on paralleling output gates

[Hal Murray]

> I am sitting here and thinking "Hey, isn't those 3 x 50 Ohm sources in
> parallel a impedance missmatch?". If you have a sufficiently long
> system (> 1/12 of the risetime in cable-length which in this case
> would mean maybe 50 cm or so) we must consider it as an impedance
> system and thus we should care less about the bulk capacitance
> behaviour (which can be "cured" with a stronger source) but rather
> with the source and load impedances relative the cable impedance.

The source impedance doesn't matter if the far end is terminated with a resistor that matches the impedance of the coax.  The main impact of those resistors is to reduce the signal swing while making sure that the load is shared by the paralleled drivers.

If the source impedance matches the transmission line, then any reflections from the far end are absorbed rather than reflected, but that only matters if there are reflections from the far end.

It's a common trick on PCBs to series terminate point to point clock lines with the impedance of the transmission line.  You get a simple 2:1 divider from the source resistor and the transmission line, so the signal goes out at half height.  When the signal gets to the far end where there isn't any termination resistor, it bounces off resulting in a full height signal.  That's what the receiving chip sees.  When that reflection gets back to the source, it sees the source termination resistor and there are no reflections.

That only works for point-to-point links.  Multi drop lines for clocks are asking for troubles at modern edge rates.




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