[time-nuts] GPS orthodontics: time averaging theory

[Dr Bruce Griffiths]

Brooke Clarke wrote:
> Hi Bruce:
>
> Thanks for the link to meta stable references.  The referenced TI paper at:
> http://www.klabs.org/richcontent/General_Application_Notes/mestablestates/meta_ti.pdf
> in Fig 10 on pdf page 13 indicates that the meta state problem is solved 
> by simply cascading a couple of D Flip-Flops.
> I think this is also what's done in the HP paper on printed page number 
> 7 in Fig. 7 Synchronizing Circuit.
>
> Have Fun,
>
> Brooke Clarke
>
> w/Java http://www.PRC68.com
> w/o Java http://www.pacificsites.com/~brooke/PRC68COM.shtml
> http://www.precisionclock.com
>
>
>
> Dr Bruce Griffiths wrote:
>
>   
>> Brooks
>>  
>>
>>     
>>>>> The "pitfalls" Dave mentions are:
>>>>>
>>>>> PARTIAL PULSE BIAS:  very narrow gated clock pulses are not counted,
>>>>> thereby introducing a bias as computed in his eq(1).   Note that all 
>>>>> the
>>>>> parameters on the right side of eq(1) are constant, thus the bias is
>>>>> constant.  A constant bias is important for a frequency counter or a 
>>>>> TIC
>>>>> since all measurements will be slightly off, but for phase locking it
>>>>> makes no difference, it just moves the phase setpoint a tiny bit.  
>>>>> Forget
>>>>> the synchronizer.
>>>>>
>>>>>        
>>>>>
>>>>>           
>>>> This analysis neglects the problem of metastable states. Whilst these
>>>> cannot be eliminated a simple shift register synchroniser can be 
>>>> employed
>>>> to reduce the metastable state rate to less than once in the age of the
>>>> universe or less if required.
>>>>      
>>>>
>>>>         
>>> I don't see that metastable states are involved since the 4520 counter 
>>> has
>>> no setup time that would compete with the 24 Mhz clock. - the 4520 input
>>> gate either passes a very narrow pulse or it doesn't.
>>>
>>>    
>>>
>>>       
>> A common misconception is that a flipflop can only enter a metastable 
>> state when the setup or hold times of the D (or J+K)  with respect to 
>> the clock are violated.
>> Perhaps the overwhelmingly common example of the possibility of 
>> metastability when using a flipflop to synchronise asynchronous data to 
>> a clock leads to this assumption.
>>
>> This assumption is incorrect, runt pulses applied to the clock input or 
>> asynchronous inputs (set, reset etc) of a flipflop can also cause 
>> metastability.
>> Every bistable circuit has a metastable state and there are many ways of 
>> attaining that metastable state.
>>
>> NASA and others believe this:
>> http://www.klabs.org/richcontent/General_Application_Notes/mestablestates/MetastableStates.htm
>>
>> Bruce
>>
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>>
>>  
>>
>>     
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>   
Brooke

If you want to save a little on the wiring just use a 74XX164 (in 
general the faster the logic family the better, however some data on the 
performance of the chosen logic family is useful as some logic families 
with equivalent speeds are better than others) or equivalent shift 
register and select the desired output.
The greater the number of stages employed the lower the rate of 
metastability at the output.
HP have on occasion used 8 bit shift registers for this purpose.
Most modern processors have built in synchronisers on their asynchronous 
inputs, but some inputs may not include synchronisers as they are not 
required with synchronous signals and only slow the processor down if 
used with synchronous input signals.

Synchronising multiple asynchronous inputs such as when one attempts to 
asynchronously read a counter on the fly requires more than just a set 
of synchronisers operating in parallel.

If you choose a logic family for which there is no data available, it is 
advisable to build a test circuit to measure its metastabilty 
characteristics.

Metastability data is available for the 74AC and 74HC  CMOS devices but 
not for the 4000 CMOS devices.

The metastability characteristics of gate arrays CPLDs etc is not 
readily available.

To veer slightly off topic it is informative to read the following on 
power up reset circuits:
http://klabs.org/DEI/References/design_guidelines/nasa_guidelines/reset/reset.htm
Just when we all thought these were simple to implement, the presence of 
charge pump bias generators and the like in gate arrays when one has 
squibs actuated by the gate array outputs, means that the performance 
and design of a power up reset circuit assumes a hitherto unprecedented 
degree of importance. Not being able to rely on the behaviour of some 
gate arrays for some time following application of power means that 
reset circuits in such cases should use simple logic devices with 
reliable powerup characteristics.

Bruce