[time-nuts] Thought experiment on a low cost timing board
phk at phk.freebsd.dk
Sat Feb 25 05:45:54 EST 2006
In message <43FDDDCD.8080002 at cloudview.com>, John Pettitt writes:
>I read the work phk did (http://phk.freebsd.dk/soekris/pps/) and came up
>with the following product idea.
>PCI 3.3v board with:
> 10Mhz OCXO (provision for external clock source?)
> Uart (serial is an endangered on many PC's)
> Free running counter driven from the OCXO and readable by PC
> inputs to latch the counter (how many?) with the latched result also
>readable (for PPS)
hehe, I did more or less exactly this five years ago.
I used a "Hot-1" card with a Xilinx 6216 from Vcc.com (now defunct).
They had an onboard PLL chip (can't remember type) so I banged the
input clock frequency up to 100 Mhz and ran a 26 bit counter (that
was as fast as it would go) and 10 latches.
You should probably aim at something similar to your clock because
100nsec resolution is pretty lumpy for PLL work.
Five of the latches had programmable dividers in front of them, so
that I could pass in frequencies, divide them down to 1Hz and
timestamp them at that rate.
One of the problems I ran into was of course noise. I found that
optocouplers generally have acceptable jitter for low quality
signals (like the mains frequency etc).
Another thing you have to be aware of is something called
'meta-stability' when you latch a signal in one synchronous clock
domain on a signal which is not in that domain. The usual trick
is to synchronize the external signal to the clockdomain through a
sequence (2-3) of latches. (the delay is constant and known, so
it can be handled in software).
Consider adding a D/A converter for tweaking OCXO. Using the two-tier
trick which SRS uses in the PRS10 may be a good and cheap way.
>So does the basic idea make sense?
Worked fine for me :-)
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
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