[time-nuts] PLL Phase Noise vs. Divider Jitter

[David Forbes]

At 5:34 PM +0200 7/8/06, Stephan Sandenbergh wrote:
>Hi All,
>
>In the previous thread, "HP 58540A Phase Noise Improvements", Matt Ettus
>noted the following:
>
>The jitter that is added by a divider would most probably pose a greater
>limit to the phase noise of the PLL than that of the specific OCXO used.
>
>Now my question: How can one divide a digital signal without using jittery
>flip-flop based counters (either discrete of those found in FPGAs)? The
>first thing that springs to mind is that of the analog pulse stretchers
>which were discussed last month. This may provide one with lower jitter but
>it would most probably increase the longer term instabilities due to
>temperature and power supply variations. What are there other alternatives?
>
>Regards,
>
>Stephan.

High frequency PLLs made for low-phase-noise applications typically 
use mixers instead of dividers. They often use a step recovery diode 
to multiply the reference to a frequency near that of the high 
frequency being measured, then mix this multiplied ref with the 
signal and run the difference frequency into the PLL.
-- 

--David Forbes, Tucson, AZ
http://www.cathodecorner.com/