[time-nuts] Linear Interpolator
df6jb at ulrich-bangert.de
Thu Jun 29 13:41:40 EDT 2006
if you need a ps resolution time interval counter for use in a project
of your own, why not simply go out and buy you one? For example here
They are not that expensive because they are made to be married with
However, you may also follow TVB's suggestion and spend some time on
finding out what resolution you really need. In
the sigma-tau-diagrams of a uncorrected M12+ pps and that of a sawtooth
corrected pps are drawn in the same diagram. Because the sawtooth
corrected pps values have a different slope the lines meet at app. Tau =
1 day. Build yourself an opinion of your own up to which tau using the
corrected values may make sense!
> -----Ursprüngliche Nachricht-----
> Von: time-nuts-bounces at febo.com
> [mailto:time-nuts-bounces at febo.com] Im Auftrag von Stephan Sandenbergh
> Gesendet: Donnerstag, 29. Juni 2006 15:20
> An: time-nuts at febo.com; 'Magnus Danielson'
> Betreff: Re: [time-nuts] Linear InterpolatorHi Stephan
> >> So you suggest, I take the 10MHz output of my OCXO lock that to a
> >> stable VCXO (say 64MHz as not to be a harmonic multiple of
> 10MHz) and
> >> then clock my FPGA with the resultant output.
> >I would rephrase that to say that you should lock your low
> jitter VCXO
> >(of say 64 MHz) to your stable OCXO (of 10 MHz).
> Thanks for correcting me. This is actually what I meant.
> >Oh, what 64 MHz oscillator do you have?
> Currently I don't have a 64MHz VCO yet. I'm just weighing my
> options. My original idea was too run the FPGA off a 64MHz
> free-running XO. This would have given me 15.6ns resolution
> with a simple start-stop type phase detector (and not too
> much EMI problems). However, in retrospect, I doubt if that
> will give me the 1ns dithered accuracy I want. It will be a
> shame to add substantial noise to the low 2ns jitter of the
> M12+T. I guess the final dithered accuracy depends on one's
> pre-averaging time.
> Well, I still think it might be better to run off a
> free-running XO to have the dithering advantage. My
> application requires good stability (ideally sub
> ns) between distant locations (maybe in the order of 100s of
> meters to 10s of kilometres) on time scales of 100s of
> seconds to a few minutes.
> I guess one can view the PLL as a very sharp roll-off
> low-pass filter. If one could have less jitter (via sawtooth
> correction and a good resolution phase detector) at the 1PPS
> input in the first place, one could set your PLL bandwidth
> higher to allow for a longer stability hold-over.
> I suppose one might be able to do the math in order to remove
> all the guess work, however I have never seen the measured
> phase noise of the M12+T's 1PPS or anything similar. So, I am
> just designing so that the M12+T, the DACs and my OCXO will
> be the limiting factors, and not the measured phase
> resolution. The reason - because it seems easy enough to do
> so. Maybe, after all, I should just go for a faster clock.
> This would allow for dithering down to about 2ns-3ns accuracy
> (same as M12+T). I'll just have to endure the EMI - keep it
> away from the sensitive circuitry etc.
> What are your thoughts? Am I just being paranoid?
> Best regards,
> time-nuts mailing list
> time-nuts at febo.com
> https://www.febo.com/cgi-> bin/mailman/listinfo/time-nuts
More information about the time-nuts