[time-nuts] How to measure Allan Deviation?
Dr Bruce Griffiths
bruce.griffiths at xtra.co.nz
Mon Oct 23 19:35:43 EDT 2006
Magnus
The drawback with a CPLD is that most have a relatively high dc supply
current.
I have a couple of CPLD designs that work the way you advocated.
A CMOS divider has the attraction that its power supply current can be
relatively small even when the (small duty cycle) output drives a 50 ohm
load.
The other problem with CPLDs is most are surface mount and use small pad
separations which can be problematic for home construction.
I have posted the pathological design to the list.
It is intended as a warning to be careful, even though one has these
nice slow low power supply noise parts in the drawer which can be used
to reliably generate a 1 PPS output, the divider will severely degrade
the measurement accuracy. It is even so pathological that one cannot
reliably resync the output to the input clock without resorting to
exceedingly expensive heroic measures such as a triple or quadruple
cascaded synchronisers (synchronising first to 100KHz output of 2nd
4017, then to the 1MHz output of the first 4017 followed by the
expensive synchroniser) The final set of synchronisers probably requires
a series of tapped delay lines that track the propagation delay of the
first divider, eventually the last synchroniser is clocked by the input
clock.
Whilst no experienced designer would even contemplate this its possible
the less experienced may fall into this trap.
Bruce
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