[time-nuts] GPS vagaries and binary interface

[Dr Bruce Griffiths]

Dr Bruce Griffiths wrote:
> Didier Juges wrote:
>   
>> Dr Bruce Griffiths wrote:
>>   
>>     
>>> Didier
>>>
>>> Alternative GPSDO solution
>>> Divide the 10MHz reference by 32 resync the output to 10MHz with a fast 
>>> D flipflop and then divide the D flipflop output by 4 using a 2 bit 
>>> switchtail ring (Johnson) counter.
>>> Low pass filter the outputs of both divide by 4 counter flipflops with 
>>> identical filters.
>>>   
>>>     
>>>       
>> OK, I follow even if I am not sure where this is leading...
>> Anything magic about 32, other than it's probably the smallest division 
>> that may not immediately result in rollover when the OCXO is cold?
>> Based on yesterday's experiment, my OCXO rolled over once while warming 
>> up with a division ratio of 128. A few more chips are not a real 
>> problem. I like the 74F161, they are fast and synchronous. If I could 
>> find 74F162's, that would be the best, or I can program the 161s as 
>> decade counters, but it's more work.
>>
>>
>>   
>>     
>>> Use ACMOS flipflops in the ring counter so the sine wave output 
>>> amplitude is reasonably stable.
>>>   
>>>     
>>>       
>> Of course, TTL outputs are anything but stable.
>>   
>>     
>>> This should produce 2 nominally quadrature sinewave outputs at (10/128) MHz.
>>> Use 2 12 bit ADCs (eg AD7942) to sample the 2 quadrature sinewaves on 
>>> the leading edge of the GPS receiver PPS signal.
>>> The ADC readings can be processed to derive the phase angle at the PPS edge.
>>> A resolution of 10ns or better is readily achieved. This is more than 
>>> adequate for most current GPS receivers.
>>> If you are worried about the stability of the low pass filter phase 
>>> shifts just use another pair of ADCs to sample the 2 sinewaves at 10/128 
>>> MHz.or a submultiple thereof.
>>> The difference between the 2 phase angles will be independent of the 
>>> filter phase shifts.
>>>
>>>   
>>>     
>>>       
>> That would be a software interpolator?
>>
>> I like that approach because it reduces the hardware to a relative 
>> minimum, compared to the Brooke Shera approach, and puts the complexity 
>> in software.
>>
>> Regarding your next message recommending to use a dual channel ADC, I 
>> agree, even though it may be simpler to use S&H devices with the 
>> built-in multiplexed ADC of the microprocessor. I have a few monolithic 
>> Burr Brown devices that have a small aperture gate, I forgot how much.
>>
>> This sounds very interesting, but it won't be an evening project :-)
>> I don't do PICs (no development tools, no code bank). I do not have the 
>> tools to do PLDs either. My favorite uCs are 8051s, particularly the 
>> Silabs parts. I also have access to a good C compiler and I have written 
>> a lot of 8051 code. I do not know how these parts fare as timing chips. 
>> They are plenty fast though, some run at a 100 MHz clock, with many 
>> instructions taking one clock.
>>
>>   
>>     
>>> Bruce
>>>
>>> _______________________________________________
>>>
>>>   
>>>     
>>>       
>> Thanks again for many thought provoking ideas.
>>
>> Didier
>>
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>>
>>   
>>     
> If they have built in hardware to sample the count of a counter on the 
> edge of an external pulse then they may be very useful.
>
> Another technique to reduce the amount of filtering required somewhat is 
> to feed a square wave of 50% duty cycle into a shift register say 12 
> bits long clocked synchronously at 8x the input square wave frequency. 
> The outputs of the first 8 stages can be added using a set of suitable 
> resistors so that a 16 step approximation to a sine wave is formed at 
> the resistor summing node. The quadrature phase sine wave can be formed 
> by resistively summing the outputs of the last 8 stages of the 12 bit 
> shift register. If the resistor values are correctly proportioned the 
> 3rd, 5th  etc harmonics can be nulled and less filtering of the sine and 
> cosine waves is required.
>
> The approximation to sine and cosine waves improves as the shift 
> register length is increased and the shift register is clocked with a 
> higher frequency synchronous clock.
> However using 2 sets of 8 resistors with a 12 bit shift register is 
> probably a reasonable compromise between the complexity of the resistor 
> arrays and the complexity of the analog low pass filters.
>
> An even better approximation is possible if a pair of DAC and a sine 
> lookup tables is employed. However the added cost and complexity is 
> probably difficult to justify.
>
> Bruce
>
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>
>   
Correction:
Oops!! The shift register should have been clocked synchronously at 16 x 
the input squarewave frequency.
The lowest harmonic in the output using zero tolerance resistors of the 
correct value is the 15th which is 24 dB below the fundamental.

This can also be done using an 8 stage Johnson counter to divide the 
input by 16.
The resistors are connected to the counter flipflop outputs.
In this case a 4 bit shift register is also required to allow the 
quadrature phase shifted signal to be generated.

For example see Figure 9.93 page 667 of Horowitz and Hill's "The art of 
electronics" (2nd edition).
However don't use their implementation of a Johnson counter using a 
shift register.
If the shift register ever starts in a state unused by the Johnson 
counter there is no provision to ensure that it will revert to a used 
state within a few clock cycles.


Bruce