[time-nuts] Gate propagation delay jitter

David Andersen dga+ at cs.cmu.edu
Mon Apr 9 01:31:07 EDT 2007


Dr Bruce Griffiths wrote:
> The attached table of logic gate propagation delay jitter should prove 
> somewhat challenging to verify with a time interval counter or similar 
> device.
> In fact devising any method of verifying these figures will be somewhat 
> problematic.
> However it could be done using by looking at the change in the output 
> noise of a high resolution pipeline ADC when such a gate is switched 
> into the sampling clock path.
> Does anyone have any other practical method of measuring such small jitter?

Depending on how much the environment affects the jitter, you could 
chain a bunch of them together and analyze the resulting distribution. 
You'd only see the tails of the distribution when the sum of the jitter 
exceeded your measurement threshold, but if you were willing to make 
some indepdence and gaussian assumptions, the analysis should be possible.

(The sum of two gaussians has variance equal to the sum of the variance 
of the input gaussians, assuming the variables are independent.  The 
thing I'd worry about is that the jitter you end up measuring is more 
affected by the environment - temp, EMI, etc.  You could correct for 
that by then measuring the variance of 2x as many chained elements;  if 
the variance was >2x, you'd know you have correlation.)

But really, I'd wager there are some very nice, known statistical 
techniques for doing this.  I'm just making something up that seems 
rational.

   -Dave




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