[time-nuts] Of rubidium life and piggy-bank anemia....

Poul-Henning Kamp phk at phk.freebsd.dk
Sat Dec 1 03:50:39 EST 2007

In message <20071201063952.93D07BE2F at ip-64-139-1-69.sjc.megapath.net>, Hal Murr
ay writes:

>Would digital inputs be good enough?  Suppose you feed several 10 MHz signals 
>into a FPGA and program it so each input signal drives a counter.  Ignoring 
>implementation details like synchronization, is that good enough to be 
>interesting?  I'm assuming you have a PC that grabs all the counters every N 

I did this 10 years ago and there are good and bad ways to do it.

"ignoring implementation details like synchronization" is like
shipping & handling: it will get you both ways.

What you want to do is this:

A master counter 26-32 bits, running off your chosen frequency source.
(mine ran 26 bit at 100 MHz in an XC6200)

For each signal, a latch that latches the master counter and can be
read out, somehow.

One pseudo-signal, that you trigger from the computer, so that you
can synchronize the computer clock with the master latch:

	t1 = getnanotime();
	tickle latch;
	t2 = getnanotime();
	read latch;
	t3 = getnanotime();
	do math of your choice.

If a source is low frequency (power-grid, 1PPS etc), just put three
latches in sequence on the signal, clocked by the master frequency,
that takes care of meta-stability.

If a source is high frequency, put an async prescaler/divider in
front of the anti-meta-stability latches.

If you are doing this on a PCI board, things are a lot simpler if
your "chosen frequency source" is the PCI clock.  But that means
that you will have to build a more elaborate mathematical model,
since you have a unstable transfer frequency.

Input noise resulted in about +/- 2LSB noise in my case, with
very rube goldberg-esque input circuits, spend some time on

Metastability will always get you +/- 1LSB noise, but it may
not be distributed evenly over that interval, so averaging is
not a perfect solution.  (Most of the assymetry is polarity
based, so you could feed the same signal to two latches on
opposite polarities and see if you can eliminate it that way).

By all means: go for it, its a very fun project.

And if you do it as a PCI card, please share the source :-)


Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG         | TCP/IP since RFC 956
FreeBSD committer       | BSD since 4.3-tahoe    
Never attribute to malice what can adequately be explained by incompetence.

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