[time-nuts] Of rubidium life and piggy-bank anemia....
phk at phk.freebsd.dk
Sat Dec 1 07:09:40 EST 2007
In message <47514D31.9040602 at xtra.co.nz>, Bruce Griffiths writes:
The signal you are trying to measure, for instance a 1PPS may
transistion right at the same time the FPGA clock does, that means
that the latch-bit may or may not make up it's mind about the
state, but usually, it will oscillate for some period.
The standard prescription for this, is to feed the input signal
through a sequence of three latch-bits, clocked by the master clock,
in order to get it synchronized to the master clock.
Once it's synchronized, you can use it to latch the counter value
without any trouble.
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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