[time-nuts] Of rubidium life and piggy-bank anemia....

Hal Murray hmurray at megapathdsl.net
Sat Dec 1 18:25:59 EST 2007


> Bad idea, you should only be using a single counter with perhaps
> multiple registers to save the count. However a using a single address
> and a FIFO can save significant time when using a microprocessor to
> read/process the stored counter samples. 

I think we may be looking at two different problems.

Your approach makes sense when looking at PPS signals.

I was thinking of looking at several 10 MHz signals.

It would be easy to convert 10 MHz to a PPS signal with a big divider.  (Some 
other scale factor may be more convenient.)

I was just going to count cycles.  No good reason, but it seemed easy to do 
and I thought/hoped it had enough information to be useful.


I was assuming the FPGA had a 100 MHz clock - anything significantly faster 
than the signal you are looking at.  First run the 10 MHz signals through a 
synchronizer.  Then bump a counter on each rising edge.

Another signal would grab copies of all the counters.  That could be either a 
poke from a PC or something handy like a PPS signal.  The PC would then read 
the counters.

If the PC does the poke, there are no timing requirements.  If the PC is slow 
you may not get what you wanted, but the data within each sample will be 
consistent.

If you do the poke with a PPS, you probably want another register that counts 
pokes.  The PC can then read it at the beginning and end of grabbing the 
data.  If the two copies are different you had timing troubles.  Dump that 
sample.  Comparing the poke-count between samples tells you when you missed 
some samples.

I was thinking of "grab" as PCI reads.  You could also send the samples out 
over RS232.  (A checksum on the line seems like a good idea.)





-- 
These are my opinions, not necessarily my employer's.  I hate spam.






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