[time-nuts] Fury Interface Board simulation results

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Dec 11 17:10:38 EST 2007


xaos wrote:
> Bruce Griffiths wrote:
>   
>> George
>>
>> In the JFET frequency doubler:
>> 1) Surely the 50 ohms should be is series with the the voltage source V3
>> for the simulation?
>>   
>>     
> Correct. I did a cut and paste "without rotate" there.
>   
>> 2) Usually a 1:4 impedance ratio step up transformer on the input is
>> about right with a similar transformer used to step down the output
>> (perhaps an even higher impedance ratio transformer (8:1, 9:1?? may be
>> better). The maximum turns ratio depends somewhat on the maximum
>> allowable drain voltage swing which in turn is limited by the drain
>> supply voltage.
>>   
>>     
> I will re-run with the this in mind and will repost.
>   
The idea is that the FETs are not operated in the square law region but
are actually switched off alternately so that the combined drain current
waveform is a rectified sinewave with a small dc offset.
With a well balanced circuit the odd harmonic amplitudes (including the
fundamental) at the output will be small with the 20MHz 4th harmonic of
the fundamental being the largest component.
Achieving low distortion isnt the aim, but achieving low phase noise is.
Any residual harmonics and subharmonics can be removed with tuned
circuit traps (dont use a high Q bandpass filter as it will inevitably
have a high phase shift tempco and may add flicker phase noise depending
on the components used). A relatively broadband low pass filter
contributes little phase shift (and associated flicker phase noise as
well as little phase shift tempco) at 10MHz as do a series of relatively
high Q LC traps. High performance is rarely achieved by the
simplest/obvious solution.
If you have difficulty finding suitable JFETs a high impedance bipolar
junction transistor (BJT) implementation is also possible however
biasing is a little trickier and requires a couple of extra BJTs to
ensure reasonable thermal stability of the bias currents.
>> In the voltage offset circuit:
>>
>> 1) The junction of R9 and R12 should be connected to the offset source
>> (+5V??).
>>   
>>     
> This is what I didn't get about the original circuit.  I was scratching 
> my head as to the purpose of a variable R9 when
> the only value that made sense was when it was set to the "0" position.
>
>   
>> I dont understand what the 7812 does in this circuit.
>>   
>>     
> It was there in the original circuit so I modeled accordingly. Actually 
> I ran some simulations with PS voltage variation
> to see the effect as well. In that case I removed the 7812.
>   
>> Isolation amplifier looks OK.
>>
>> Bruce
>>   
>>     
> This is a very nice design and the AC analysis shows a bandpass around 
> 10 MHz with 20 MHz BW.
>
> The only issue I see there is that it needs 50 parts of 6 different values.
>
> This might be difficult to implement on a small board and would be prone 
> to error for people trying to
> assemble their own board.
>
> The way I see the final product is a bare board and possibly a kit. It 
> has to be easy to assemble and minimize
> errors.
>
> Actually, I was looking at the isolation amplifier provided in the C.M. 
> Felton Paper:
>
> http://www.darksmile.net/ee/Superimposing_Low-Phase-Noise_Low-Drift_Instrumentation_Techniques_On_RF_Design.pdf
>
> It is relatively simple and would use similar devices as the Frequency 
> doubler.
>   
The trouble with this design is that it has a low input impedance and
thus is unsuitable for OCXOs that require a high impedance load (eg 10544A).
Its gain isnt adjustable and its difficult to obtain suitable dual JFETS
(you would have to use a couple of J310's to achieve similar performance
since U431 isnt readily obtainable, the LS840 is definitely unsuitable
as its minimum Idss isnt high enough ), it also has relatively low
reverse isolation. Simplicity isnt the key to high performance.
> I will upload more info as I compile it.
>
> George
>   




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