[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?

[Bruce Griffiths]

Scott Burris wrote:
>
> Yes!  I now feel inspired to go spin a design after studying all of 
> these messages in this
> thread.  My only constraint is that the parts have to pass the "Digikey" 
> test, i.e. I have to
> be able to order small quantities from Digikey, Mouser, or the like.  
> It's nearly impossible
> for a hobbyist like me to get small quantities of more exotic parts.  
> The big distributors have
> gotten better in the last decade about taking small orders, but still 
> often have minimum qty/piece
> requirements that they won't waive.  Even worse are orderable, but 
> unobtainable parts -- Maxim
> seems to have a huge library of such "virtual" chips that have lead 
> times of 1/2 year or more.
>
> Scott
>   
Scott

On checking the Mouser and Digikey websites the DS1020 series
programmable delay lines are non stock items.
However I can obtain the DS1020-25 locally from RS Components.
The D1020-15 would be preferable for use with an M12M GPS timing
receiver, however the DS1020-25 could be used.

Maybe we need to consider using a CPLD or another implementation (eg
ramp generator plus DAC (8bit) and comparator).
Analog Devices used to make a single chip implementation of the ramp
plus DAC and comparator programmable delay system.
However such devices need to be calibrated, preferably continuously.
The saving grace is that with a dedicated processor, there's plenty of
time and processing power to do this once a second (between successive
PPS pulses).

Calibration technique is simple:

1) Adjust the programmed delay so that the programmed delay is exactly 1
(OCXO) clock period record the DAC data required to achieve this.

2) Adjust the programmed delay so that the programmed delay is exactly 2
(OCXO) clock periods, record the DAC data required to achieve this.

3) calculate the OFFSET and GAIN parameters from the above data.

Of course such a scheme can be elaborated to include delays greater than
a couple clock periods and exponential averaging of results can be
employed to reduce the noise.
The calibration technique assumes that the delay is a linear function of
the DAC input.
A D flipflop plus some additional logic (synchroniser) can be used to
detect coincidence between the clock edge and the output of the delay
device.

Bruce