[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?
bruce.griffiths at xtra.co.nz
Thu Dec 13 02:57:39 EST 2007
michael taylor wrote:
> On Dec 12, 2007 2:32 AM, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
>> The analog circuitry for a sigma-delta DAC is attached.
>> The input is optically isolated using a high speed low jitter CMOS
>> optocoupler (Avago produce an equivalent device) to break low frequency
>> ground loops.
> I was wondering if the Avago HCPL-9000 or Analog's ADUM1100 iCoupler
> would be suitable alternatives to the HCPL-7100.
Check the jitter, no jitter specs given for the iCouplers.
You may have to measure it on a sample.
The HCPL9000 should be fine but measure the jitter.
Circuit is actually reasonably tolerant to jitter as the low pass filter
averages such effects over many cycles.
If jitter proves a problem then if the micro or other logic generating
the sigma delta DAC bit-stream is clocked by the OCXO a D flipflop can
be used to retime the bitstream after the optocoupler/isolator reducing
the bit stream jitter to a few tens of picoseconds or so.
>> Similarly an RF transformer should be used to couple the OCXO output to
>> the Digital board breaking another potential low frequency ground loop.
> For the RF transformer I am considering a Coilcraft WB1-6(S)L
> transformer to decouple the OCXO output.
Probably OK although there appear to be no VSWR specs for these.
> I want to do some more reading, but I think I'm might have some
> questions about DAC input data (from the microprocessor).
> Would there be any problems, or benefits to using AHC versus AC logic
> family flipflops and the inverting Schmitt triggers?
Whilst HC logic performance is adequate there is probably not too much
harm in using AHC or even AC as long as you use a ground plane together
with suitable layout techniques.
Metastability rates would go down by a large factor however the rate
with HC logic should be well below once every 1E10 years.
> In regards to the sawtooth correction, I am undecided. If I understand
> correctly, even without not addressing it there should be an
> improvement over existing public designs (Shera, Miller). If I
> remember correctly, you were keen on a software/firmware based
> sawtooth approach, if so that might be more flexible and cheaper than
> fiddling with a uncalibrated DS1020 delay line.
Depends on the entire system cost a single chip programmable delay plus
a D flipflop and little else should be cheaper than most high resolution
phase detector approaches.
As long as one can calibrate the DS1020 to improve its performance over
the datasheet specs. If it is sufficient to do this once (using a 5370
or equivalent) then the cost may be lower.
There are a lot of legacy devices/systems in use that actually require a
low jitter PPS pulse.
Most phase detectors with resolution, stability and accuracy better than
1ns (needs to be better than 500ps or so avoid significantly degrading
the quality of the correction) also require calibration unless one has a
suitable (2??) GHz clock (or equivalent) locked to the OCXO being
1ns accuracy and stability are perhaps easier to achieve when using a
sampled quadrature pair sine wave interpolator but even this requires
significant support logic to facilitate measuring harmonic content ,
quadrature error etc.
> Thank you,
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