[time-nuts] Metastability in a 100 MHz TIC

[Richard H McCorkle]

In my Brooks Shera style LPRO rubidium controller I am using
the same HC4046 input conditioner and divide down counter on
the oscillator and HC4046 phase detector interrupting the PIC
as used in the original design. The phase detector output
feeds the count enable input of a pair of Fairchild 74F163A
synchronous binary counters clocked with a 100 MHz XO to
increase the TIC sample resolution to 10ns. The counters are
read and cleared every second and accumulated in software to
minimize glitches from multiple gating into the counter. A
23-bit DAC and LM199 reference are used to improve the EFC
resolution, applying 0-5v directly to the LPRO EFC input to
minimize noise pickup and maximize loop gain. A 16F688 PIC
monitors the GPS messages and accumulates sawtooth corrections
until read at the update time over a high-speed 200kbps
3-wire handshaking serial interface by the 16F873A main
controller. The handshaking interface allows the 16F688 to
transmit the accumulated sawtooth correction for the current
sample to the controller and reset its accumulator between UART
reads to prevent data loss and before the TRAIM message for
the next sample arrives to insure the predictions match the
samples.
   A 4x larger setpoint and 1/4 the filter gain of the original
design are used to adjust for the larger counts returned with
a 100 MHz TIC. This keeps the controller gain and limiting
threshold approximately the same as the original design to
prevent excessive limiting of the input data into the filter
at high phase offsets and maintains good initial lock
performance. Since the 1-second stability of a rubidium
oscillator is relatively poor, and the 100-second stability
is much better, the loop update time was increased in the
rubidium controller from 30 to 120 seconds. The longer update
time results in 1/4 the number of updates to the EFC for
improved stability, and 4x more samples accumulated per update
to provide a better indication of true rubidium oscillator
stability. Without increasing the controller gain and using
a TIC with 4x the resolution of the original design over a
sample period 4x longer than the original design the loop gain
is 16x greater than the original design for proper loop
damping with the rubidium oscillator.
   I originally assumed the 4x longer filter times that result
with the longer update time would be an advantage with a
rubidium oscillator. Testing revealed that proper correction
for daily temperature variations prevented using filter modes
with settle times longer than about half a day, or what the
Mode 7 (Tau = 8K sec) IIR filter in the original design
provides. The longer update time made the top two filter
modes settle in about 1 and 2 days and were not fast enough
in correcting for temperature variations to maintain optimum
long-term stability. Adjusting the mode scaling to 1/4 the
original value to compensate for the longer update time
restored the original range of IIR filter times.
   With the discussions here on metastable states in TIC
counters, I am asking the experts on the list for their
opinion if the performance of this design would improve
by adding a shift register synchronizer between the phase
detector output and the count enable input of the 74F163A
TIC to reduce metastable states. The 74F series has the
best reliability figures from metastable effects of all
the TTL logic families according to the data I have read.
Each D F/F counter cell in the 74F163A has the clock applied
directly to the F/F, so no clock gating occurs. Instead the
input data is gated by count enable signals for each cell and
either the cell output is sent to the D input if the count
enable is low, or the previous cell output is gated into the
D input on carry if the count enable is high with D latched
into all F/Fs on each clock rising edge. While I see the need
for a synchronizing shift register in a gated clock design
like the original Shera controller, is it necessary for best
performance in a GPSDRO application with a 74F163A 100 MHz TIC?