[time-nuts] Low noise frequency multiplication
SAIDJACK at aol.com
SAIDJACK at aol.com
Thu Mar 1 20:55:58 EST 2007
In a message dated 3/1/2007 13:30:26 Pacific Standard Time,
die at dieconsulting.com writes:
I had never thought about relative performance issues of using a
VCXO locked with a really narrow band PLL to a lower frequency reference
versus a multiplier with a narrow band cleanup filter at the output...
other than to realize that unless one uses a more complex PLL design
really narrow band loops implemented extremely straightforwardly
(perhaps to the point of idiocy) require the higher frequency VCXO to be
accurately on frequency within the low pass bandwidth else the loop
won't capture. This gets a bit dicey if one is talking 1 Hz or less at
this is not necessarily as complicated as you mention. If you use a simple
Exor gate as the phase comparator with the 100MHz (or 1GHz) divided down to
10MHz, then there is no dependency between the loop bandwidth to the frequency
of the VCXO. It will simply lock, no matter how slow the loop bandwidth (of
course the bandwidth has to be faster than thermal, and aging effects on the
VCXO since this is what you would like to compensate for with the PLL).
The Exor gate won't have a problem in locking onto harmonics etc of the
reference since the VCXO has a very small control frequency range.
You do have to make sure that the VCXO adjustment range is sufficient to
allow it to always lock to the reference, taking long-term crystal aging etc
For a sample VCXO that can be driven by a simple Exor gate as the phase
comparator see also:
The cleanup filter is a simple second-order 25Hz cut-off RC, and it only has
to remove the 10MHz phase comparison output from the Exor gate. No
relationship between loop bandwidth and output frequency.
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